1. A computer-implemented method for debugging a map-reduce application on a cluster comprising:
(A) defining a cluster of two or more computers by:
(1) installing a map-reduce framework onto each of the two or more computers, wherein the map-reduce framework comprises an integrated development environment (IDE); and
(2) formatting the cluster by:
(i) identifying the two or more computers in the cluster;
(ii) establishing communication between the two or more computers; and
(iii) enabling the cluster of two or more computers to function as a unit;
(B) placing data into the cluster;
(C) obtaining a function to be executed by the map-reduce framework on the cluster; and
(D) debugging the function directly on the cluster using the IDE, wherein the function being debugged is directly executed on the cluster using the data in the cluster, wherein the debugging further comprises:
(1) dynamically accepting code for the function that is input into a debugger of the IDE;
(2) dynamically determining, as the code is dynamically typed into the debugger, if the code specifies a heap allocation without reusing memory; and
(3) if the code specifies a heap allocation without reusing memory, dynamically highlighting the code in the debugger.
2. The computer-implemented method of claim 1, wherein the formatting identifies all of the computers in the cluster as well as the computer that the formatting command is being issued from.
3. The computer-implemented method of claim 1, wherein the debugging is initialized on any of the two or more computers without regard to functionality available on the two or more computers.
4. The computer-implemented method of claim 1, further comprising providing, as part of the IDE, a skip to reduce function configured to skip a map portion of the map-reduce function during the debugging.
5. The computer-implemented method of claim 1, further comprising utilizing a scroll widget that is configured to specify a location in the data to begin the debugging.
6. The computer-implemented method of claim 1, wherein the function is obtained by dynamically developing the function as part of the IDE using a just-in-time compiler that compiles code of the function at execution time.
7. The computer-implemented method of claim 1 further comprising accepting an alternative string data type for the data in the cluster, wherein the alternative string data type reuses its own memory stack within the IDE.
8. An apparatus for debugging a map-reduce application on a computer cluster comprising:
(A) a computer cluster comprising two or more computers;
(B) a map-reduce framework installed onto each of the two or more computers, wherein:
(1) the map-reduce framework defines the cluster;
(2) the map-reduce framework comprises an integrated development environment (IDE); and
(3) the cluster is formatted by:
(i) identifying the two or more computers in the cluster;
(ii) establishing communication between the two or more computers; and
(iii) enabling the cluster of two or more computers to function as a unit;
(C) data that is placed into the cluster; and
(D) a function configured to be executed by the map-reduce framework on the cluster; and
(E) a debugger that is part of the IDE, wherein:
(1) the function is debugged directly on the cluster using the debugger; and
(2) the function being debugged is directly executed on the cluster using the data in the cluster;
(3) the debugger is configured to dynamically accept code for the function that is input into a debugger of the IDE;
(4) the debugger is configured to dynamically determine, as the code is dynamically typed into the debugger, if the code specifies a heap allocation without reusing memory; and
(5) if the code specifies a heap allocation without reusing memory, the debugger is configured to dynamically highlight the code in the debugger.
9. The apparatus of claim 8, wherein the cluster is formatted by identifying all of the computers in the cluster as well as the computer that the formatting command is being issued from.
10. The apparatus of claim 8, wherein the debugger is initialized on any of the two or more computers without regard to functionality available on the two or more computers.
11. The apparatus of claim 8, wherein the debugger comprises a skip to reduce function configured to skip a map portion of the map-reduce function during the debugging.
12. The apparatus of claim 8, wherein the debugger comprises a scroll widget that is configured to specify a location in the data to begin the debugging.
13. The apparatus of claim 8, wherein the function is obtained by dynamically developing the function as part of the IDE using a just-in-time compiler that compiles code of the function at execution time.
14. The apparatus of claim 8, wherein the debugger is further configured to accept an alternative string data type for the data in the cluster, wherein the alternative string data type reuses its own memory stack within the IDE.
15. A system for debugging a map-reduce application on a cluster comprising:
(A) two or more computers communicatively coupled to each other to define a cluster that functions as a unit;
(B) a map-reduce framework installed on each of the two or more computers, wherein the map-reduce framework comprises an integrated development environment (IDE);
(C) a function configured to be executed by the map-reduce framework on data in the cluster;
(D) a debugger installed as part of the IDE, wherein the debugger is configured to:
(1) debug the function directly on the cluster;
(2) dynamically accept code for the function that is input into a debugger of the IDE;
(3) dynamically determine, as the code is dynamically typed into the debugger, if the code specifies a heap allocation without reusing memory; and
(4) if the code specifies a heap allocation without reusing memory, dynamically highlight the code in the debugger.
16. The system of claim 15, wherein a debug operation is initialized on the debugger on any of the two or more computers without regard to functionality available on the two or more computers.
17. The system of claim 15, wherein the debugger further comprises, a skip to reduce function configured to skip a map portion of the map-reduce function during a debugging operation.
18. The system of claim 15, wherein the debugger further comprises a scroll widget that is configured to specify a location in the data to begin the debugging.
19. The system of claim 15, wherein the function is obtained by dynamically developing the function as part of the IDE using a just-in-time compiler that compiles code of the function at execution time.
20. The system of claim 15, wherein the debugger is further configured to accept an alternative string data type for the data in the cluster, wherein the alternative string data type reuses its own memory stack within the IDE.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A radio frequency mixer system comprising:
a four phase clock generator to generate four phased half duty cycle clocks of the same frequency and each being out of phase by a multiple of ninety degrees from the others;
a dual differential electrical load having a first differential input and a second differential input; and
a four phase half duty cycle mixer comprising a differential input port coupled to a differential input signal, an in-phase (I) differential output port coupled to the first differential input of the dual differential load, and a quadrature-phase (Q) differential output port coupled to the second differential input of the dual differential load, wherein the mixer comprises a plurality of first level switches coupled in parallel to the differential input port and a corresponding plurality of pairs of parallel second level switches, each pair of parallel second level switches coupled in series to one respective first level switch and to the dual differential output port, said first level and second level switches comprising control inputs coupled to the four phase clock generator to receive the four phased half duty cycle clocks, wherein the control inputs of the first level switches are connected to first and second clock phases and the control inputs of the second level switches are connected to third and fourth clock phases, and wherein the mixer is configured to convolve the differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal on the in-phase differential output port and a differential quadrature-phase output signal on the quadrature-phase differential output port.
2. The radio frequency mixer system of claim 1, further comprising:
a differential signal source having a differential output coupled to the differential input port of the four phase half duty cycle mixer, the differential signal source to generate the differential input signal in response to a non-differential input signal.
3. The radio frequency mixer system of claim 1, wherein
the differential input signal is a radio frequency differential input signal,
the differential in-phase output signal is an intermediate frequency differential in-phase output signal, and
the differential quadrature-phase output signal is an intermediate frequency differential quadrature-phase output signal.
4. The radio frequency mixer system of claim 1, wherein
the differential input signal is an intermediate frequency differential input signal,
the differential in-phase output signal is a radio frequency differential in-phase output signal, and
the differential quadrature-phase output signal is a radio frequency differential quadrature-phase output signal.
5. The radio frequency mixer system of claim 1, wherein the plurality of first level switches and the corresponding plurality of pairs of parallel second level switches are a first type of transistor closed by the application of a high voltage level upon its control terminal and opened by the application of a low voltage level upon its control terminal, a second type of transistor closed by the application of a low voltage level upon its control terminal and opened by the application of a high voltage level upon its control terminal, or a combination of the first transistor type and the second transistor type.
6. A radio frequency mixer comprising:
a plurality of first level switches comprising first control inputs and coupled in parallel to a differential input port;
a corresponding plurality of pairs of parallel second level switches comprising second control inputs and each pair of parallel second level switches coupled in series to one respective first level switch and to a dual differential output port; and
wherein the plurality of first level switches and the corresponding plurality of pairs parallel second level switches are configured to receive four phased half duty cycle clocks of the same frequency and each being out of phase by a multiple of ninety degrees from the others, and wherein the first control inputs are connected to first and second clock phases and the second control inputs are connected to third and fourth clock phases to convolve a differential input signal on the differential input port with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on the dual differential output port.
7. The radio frequency mixer of claim 6, wherein
the differential input signal is a radio frequency differential input signal,
the differential in-phase output signal is an intermediate frequency differential in-phase output signal, and
the differential quadrature-phase output signal is an intermediate frequency differential quadrature-phase output signal.
8. The radio frequency mixer of claim 6, wherein
the differential input signal is an intermediate frequency differential input signal,
the differential in-phase output signal is a radio frequency differential in-phase output signal, and
the differential quadrature-phase output signal is a radio frequency differential quadrature-phase output signal.
9. The radio frequency mixer of claim 6, wherein the plurality of first level switches and the corresponding plurality of pairs of parallel second level switches are a first type of transistor closed by the application of a high voltage level upon its control terminal and opened by the application of a low voltage level upon its control terminal, a second type of transistor closed by the application of a low voltage level upon its control terminal and opened by the application of a high voltage level upon its control terminal, or a combination of the first type of transistor and the second type of transistor.
10. A method comprising:
generating four phased half duty cycle clocks of the same frequency and each being out of phase by a multiple of ninety degrees from the others;
coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and
switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port, and wherein the switching comprises:
switching the differential input signal based on first and second clock phases to generate first level switching outputs; and
switching the first level switching outputs based on third and fourth clock phases using a plurality of pairs of second level switches to generate the differential in-phase output signal and the differential quadrature-phase output signal on the dual differential output port;
wherein each pair of second level switches receives one first level switching output.
11. The method of claim 10, wherein said switching comprises:
in response to a first phase of the four phased half duty cycle clocks,
closing a first 1st level switch and a first 2nd level switch coupled in series to the first 1st level switch to pass through a signal on a positive RF input terminal to a positive in-phase output terminal coupled into a first differential load, and
closing a third 1st level switch and a fifth 2nd level switch coupled in series to the third 1st level switch to pass through a signal on a negative RF input terminal to a negative in-phase output terminal coupled into the first differential load;
in response to a second phase of the four phased half duty cycle clocks,
closing the first 1st level switch and a second 2nd level switch coupled in series to the first 1st level switch to pass through a signal on a positive RF input terminal to a positive quadrature-phase output terminal coupled into a second differential load, and
closing the third 1st level switch and a sixth 2nd level switch coupled in series to the third 1st level switch to pass through a signal on a negative RF input terminal to a negative quadrature-phase output terminal coupled into the second first differential load;
in response to a third phase of the four phased half duty cycle clocks,
closing a second 1st level switch and a third 2nd level switch coupled in series to the second 1st level switch to pass through a signal on a positive RF input terminal to a negative in-phase output terminal coupled into the first differential load, and
closing a fourth 1st level switch and a seventh 2nd level switch coupled in series to the fourth 1st level switch to pass through a signal on a negative RF input terminal to a positive in-phase output terminal coupled into the first differential load; and
in response to a fourth phase of the four phased half duty cycle clocks,
closing the second 1st level switch and a fourth 2nd level switch coupled in series to the second 1st level switch to pass through a signal on a positive RF input terminal to a negative quadrature-phase output terminal coupled into the second differential load, and
closing the fourth 1st level switch and an eighth 2nd level switch coupled in series to the fourth 1st level switch to pass through a signal on a negative RF input terminal to a positive quadrature-phase output terminal coupled into the second differential load.
12. The method of claim 10, wherein each of the switches is an n-channel field effect transistor (NFET) closed by the application of a high voltage level upon its gate terminal.
13. The method of claim 10, wherein each of the switches is a p-channel field effect transistors (PFET) closed by the application of a low voltage level upon its gate terminal.
14. The method of claim 10, wherein each of the switches is a p-channel field effect transistors (PFET) and an n-channel field effect transistors (NFET) coupled in parallel together, the PFET being closed by the application of a low voltage level upon its gate terminal and the NFET being closed by the application of a high voltage level upon its gate terminal.
15. An apparatus comprising:
means for generating four phased half duty cycle clocks of the same frequency and wherein each of the four phased half duty cycle clocks are out of phase by a multiple of ninety degrees from the others;
means for convolving a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port, and wherein the means for convolving comprises:
means for switching the differential input signal based on first and second clock phases to generate first level switching outputs; and
means for switching the first level switching outputs based on third and fourth clock phases using a plurality of pairs of second level switches to generate the differential in-phase output signal and the differential quadrature-phase output signal on the dual differential output port; and
means for coupling the four phased half duty cycle clocks into the means for convolving
wherein each pair of second level switches receives one first level switching output.
16. The apparatus of claim 15, wherein the means for coupling the four phased half duty cycle clocks comprises conductive traces in one or more layers of an integrated circuit.
17. The apparatus of claim 15, wherein the means for convolving comprises a four phase half duty cycle mixer including a plurality of first level switches coupled in parallel that each first level switch is coupled in series to a corresponding pair of parallel second level switches that are switched in response to the four phased half duty cycle clocks.
18. The apparatus of claim 15, wherein the means for generating the four phased half duty cycle clocks comprises a clock generator.
19. The apparatus of claim 15, wherein
the differential input signal is a radio frequency differential input signal,
the differential in-phase output signal is an intermediate frequency differential in-phase output signal, and
the differential quadrature-phase output signal is an intermediate frequency differential quadrature-phase output signal.
20. The apparatus of claim 15, wherein
the differential input signal is an intermediate frequency differential input signal,
the differential in-phase output signal is a radio frequency differential in-phase output signal, and
the differential quadrature-phase output signal is a radio frequency differential quadrature-phase output signal.