What is claimed is:
1. An adjustable biased Gamma-correction circuit for the purpose of forming a plurality of plus and minus driving voltages based on a central voltage, comprising:
a plurality of symmetrical dividing voltage units, each symmetrical dividing voltage unit including a serial connection of a first resistor having a resistor value, a varistor, and a second resistor having said resistor value between a first input terminal and a second input terminal, an input of a first buffer connected at a first end of said varistor, and an input of a second buffer connected at a second end of said varistor for respectively generating a pair of said plus driving voltage and said minus driving voltage from an output of said first buffer and an output of said second buffer; and
wherein said output of said first buffer and said output of said second buffer of each symmetrical dividing voltage unit are connected respectively to said first input terminal and said second input terminal of said next symmetrical dividing voltage unit, and said first input terminal and said second input terminal of said first symmetrical dividing voltage unit are connected respectively to a first voltage and a second voltage.
2. An adjustable biased Gamma-correction circuit for the purpose of forming a plurality of plus and minus driving voltages based on a central voltage, comprising:
a plurality of symmetrical dividing voltage units, each symmetrical dividing voltage unit including a serial connection of a first resistor having a resistor value, a resistor value control circuit, and a second resistor having said resistor value between a first input terminal and a second input terminal, an input of a first buffer connected at a first end of said resistor value control circuit, and an input of a second buffer connected at a second end of said resistor value control circuit for respectively generating a pair of said plus driving voltage and said minus driving voltage from an output of said first buffer and an output of said second buffer; and
wherein said output of said first buffer and said output of said second buffer of each symmetrical dividing voltage unit are respectively connected to said first input terminal and said second input terminal of said next symmetrical dividing voltage unit, and said first input terminal and said second input terminal of said first symmetrical dividing voltage unit are respectively connected to a first voltage and a second voltage.
3. The circuit according to claim 2, wherein a control terminal of said resistor value control circuit can change a resistance value connected between said first resistor and said second resistor.
4. The circuit according to claim 3, wherein said resistor value control circuit is a field effect transistor, and a drain of said field effect transistor is connected to said input of said first buffer, a source of said field effect transistor is connected to said input of said second buffer, and a gate of said field effect transistor is said control terminal for controlling said resistor value between said source and said drain.
5. The circuit according to claim 3, wherein said resistor value control circuit is a field effect transistor, and a source of said field effect transistor is connected to said input of said first buffer, a drain of said field effect transistor is connected to said input of said second buffer, and a gate of said field effect transistor is said control terminal for controlling said resistor value between said source and said drain.
6. An adjustable biased Gamma-correction circuit for the purpose of forming a plurality of plus and minus driving voltages based on a central voltage, comprising:
a plurality of symmetrical dividing voltage units, each symmetrical dividing voltage unit including a varitor having a drawing terminal connected between an input terminal and a first voltage, a first amplifier having said drawing terminal connected to a plus input of said first amplifier and a minus input of said first amplifier connected to an output of said first amplifier, a second amplifier having a first resistor having a resistor value connected between said minus input of said first amplifier and a minus input of said second amplifier and a second resistor having said resistor value connected between said minus input of said second amplifier and an output of said second amplifier and said central voltage connected to a plus input of said second amplifier for respectively generating a pair of said plus driving voltage and said minus driving voltage from said output of said first amplifier and said output of said second amplifier; and
wherein said output of said first amplifier of each symmetrical dividing voltage unit is connected to said input terminal of said next symmetrical dividing voltage unit, and said first input terminal is connected to a second voltage.
7. The circuit according to claim 6, wherein said first amplifier is an operation amplifier.
8. The circuit according to claim 6, wherein said second amplifier is an operation amplifier.
9. The circuit according to claim 6, wherein said first voltage is a voltage source and said second voltage is a ground voltage.
10. The circuit according to claim 6, wherein said first voltage is a ground voltage and said second voltage is a voltage source.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fin field effect transistor (FinFET) memory cell comprising:
a substrate for providing mechanical support;
a first dielectric layer overlying the substrate;
a fin structure overlying the dielectric layer and comprising a first current electrode and a second current electrode separated by a channel;
a floating gate comprising a vertical portion that is adjacent to and electrically insulated from a side of the channel and comprising a horizontal portion overlying the first dielectric layer and extending laterally away from the channel, the floating gate storing electrical charge;
a second dielectric layer adjacent the floating gate; and
a control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer.
2. The fin field effect transistor memory cell of claim 1 wherein the vertical portion of the floating gate is substantially perpendicular with the horizontal portion to form an \u201cL\u201d shaped floating gate.
3. The fin field effect transistor memory cell of claim 1 wherein the horizontal portion of the floating gate is at least one-third as long as the vertical portion of the floating gate is tall.
4. The fin field effect transistor memory cell of claim 1 wherein the first dielectric layer comprises a first electrically insulating material and the second dielectric layer both comprise oxide.
5. The fin field effect transistor memory cell of claim 1 wherein a capacitance between the horizontal portion of the floating gate and the control gate comprises at least ten percent of capacitance between the vertical portion of the floating gate and the control gate.
6. A method of forming a device comprising:
providing a substrate for providing mechanical support;
forming a first dielectric layer overlying the substrate;
forming a fin structure overlying the dielectric layer by forming a first current electrode and a second current electrode separated by a channel;
forming a floating gate for storing electrical charge comprising a vertical portion that is adjacent to an electrically insulating layer on a side of the channel and comprising a horizontal portion overlying the first dielectric layer and extending laterally away from the channel;
forming a second dielectric layer adjacent the floating gate; and
forming a control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer.
7. The method of claim 6 further comprising:
forming a sacrificial dielectric spacer for use as a mask to protect the horizontal and vertical portions of the floating gate during a selective etch of exposed portions of floating gate material when forming the floating gate.
8. The method of claim 7 wherein the selective etch electrically isolates the device from any adjoining devices.
9. The method of claim 6 further comprising:
implementing the insulating layer and the second dielectric layer with different dielectric materials wherein the insulating layer is formed by growing a thermal oxide and the second dielectric layer is formed by a deposition of a combination of oxide and nitride layers.
10. The method of claim 6 further comprising:
forming the vertical portion of the floating gate substantially perpendicular to the horizontal portion to form an \u201cL\u201d shaped floating gate.
11. The method of claim 6 wherein forming the first current electrode and the second current electrode further comprise:
implanting a predetermined dopant into the fin structure while protecting the channel of the fin structure using the control gate.
12. The method of claim 6 further comprising:
forming the fin structure with a height substantially in a range of fifty nanometers to two hundred nanometers.
13. A method of forming a fin field effect memory cell, comprising:
providing a substrate;
forming a fin structure comprising a channel and source and drain regions that are separated by the channel;
forming a floating gate for storing charge within the fin field effect memory cell, the floating gate being electrically isolated from and laterally adjacent to the channel by a first distance, the floating gate further comprising a vertical portion extending substantially from a base to a top of the fin structure and comprising a horizontal portion extending laterally from the vertical portion at the base of the fin structure and overlying the substrate; and
forming a control gate insulated from and adjacent to the floating gate on a first side of the floating gate that is opposite from a second side adjoining the channel.
14. The method of claim 13 wherein forming the floating gate further comprises:
forming a sacrificial dielectric spacer for use as a mask to protect the vertical portion and the horizontal portion of the floating gate;
selectively etching exposed portions of floating gate material of the floating gate; and
removing the sacrificial dielectric spacer.
15. The method of claim 14 further comprising:
insulating the fin structure from the substrate with a first insulating layer; and
implementing the first insulating layer and the sacrificial dielectric spacer with different dielectric materials wherein the sacrificial dielectric spacer etches at a faster rate than the first insulating layer.
16. The method of claim 13 further comprising:
forming the fin structure with a height substantially in a range of fifty nanometers to two hundred nanometers.
17. The method of claim 13 further comprising:
forming the horizontal portion of the floating gate at least one-third as long as the vertical portion of the floating gate is tall.
18. The method of claim 13 further comprising:
implanting a predetermined dopant into the fin structure while protecting the channel of the fin structure using the control gate.
19. The method of claim 13 further comprising:
forming the vertical portion of the floating gate substantially perpendicular to the horizontal portion to form an \u201cL\u201d shaped floating gate.
20. The method of claim 13 further comprising:
forming the horizontal portion of the floating gate to have a length sufficient so that a first capacitance value between the control gate and the floating gate is greater than a second capacitance value between the channel and the floating gate.