What is claimed is:
1. A leg direction-control mini-tricycle comprising a front frame and a rear frame; wherein
the front frame has a front wheel fork and a pedal fork; a lower end of the front wheel fork has a front wheel spindle; the front wheel spindle is pivotally connected to a front wheel and a follower; the follower is fixedly connected to a front wheel; a lower end of the front wheel fork is connected to a lower end of the pedal fork; an upper end of the pedal fork is connected with a pedal seat; a pedal shaft is pivotally installed to the pedal seat; the pedal shaft is fixed with a driving means; a driven means serves to connect the driving means and the follower; each of two ends of the pedal shaft is connected to one end of a crank; another end of each crank is pivotally connected to a pedal; and a stand shaft is connected to an upper end of the front wheel fork; and
the rear frame has a sleeve which is pivotally connected to the stand shaft; an L shape seat frame is connected with the sleeve; a top of the seat frame has a cushion; and a lower end of the seat frame is pivotally connected with a pair of rear wheels
2. The leg direction-control mini-tricycle as claimed in claim 1, wherein a handle seat is connected to an upper end of the front wheel fork; and each of two ends of the handle seat is extended with a handle; the handle is foldable; the handle seat is installed at an upper or an lower side of the stand shaft; and the handle seat is installed with a brake.
3. The leg direction-control mini-tricycle as claimed in claim 2, wherein the handles are connected to the handle seat through quick detaching means; each of two ends of the handle seat has a slot; one end of each handle is an embedding piece for being embedded into the slot; one spindle of the quick detaching means passes through the handle seat and the handle; one control arm of the quick detaching means is connected to one end of the spindle and another end of the spindle is an enlarged end.
4. The leg direction-control mini-tricycle as claimed in claim 1, wherein a crank positioning seat is connected between the crank and the pedal shaft; the crank positioning seat has an axial hole and a positioning slot; the pedal shaft inserts into the axial hole and then a fixing shaft is used to fix the crank positioning seat and the pedal seat; after the crank inserts into the positioning slot, a rotary shaft penetrates therethough and then fixes the crank and the rotary shaft; an opening is formed on the crank; the crank positioning seat has a penetrating hole out of the position slot; a frame body protrudes from the penetrating hole; a crank tenon passes through the frame body, the penetrating hole and the opening positions the crank; when the crank tenon is pulled out, the crank rotates through 180 degrees, and then pushes the crank tenon into the opening and the penetrating hole so that the crank is repositioned.
5. The leg direction-control mini-tricycle as claimed in claim 1, wherein the cushion has a lifting handle.
6. The leg direction-control mini-tricycle as claimed in claim 1, wherein each of the rear wheels is connected to one end of a swing arm; and another end of the swing arm is pivotally connected to a seat frame; a lower end of the seat frame is an arm portion; two ends of the arm portion have respective openings of the swing arm; a rear side of the arm portion is folded downwards as a sealing side; a front side of the arm portion is an open end; a pair of arm tenons are formed on the arm portion; each arm tenon has an engaging hole; the arm portion has a pair of guiding rods; the engaging holes of the arm tenon is inseted by the guiding rods so that a suspending end of the swing arm resists against the opening of the swing arm; when the tenon of the swing arm moves upwards, the swinging arm rotates forwards; and the rear wheel is closed through rotation.
7. The leg direction-control mini-tricycle as claimed in claim 1, wherein the driving means is a driving chain wheel and the follower is a driven wheel; and the driven means is a chain.
8. The leg direction-control mini-tricycle as claimed in claim 1, wherein the front wheel is electrically driven by an electromotive means, the electromotive means is formed by a battery, a motor, a driven element and a driven wheel, the driven wheel is installed at one side of a front wheel so that the driven wheel and the front wheel are engaged with the wheel shaft; the battery supplies power to the motor; a power out shaft of the motor is engaged with the driven element and the driven element is engaged with the driven wheel; thus, when the motor rotates, the power output shaft, driven element, and the driven wheel are driven so as to rotate the front wheel.
9. The leg direction-control mini-tricycle as claimed in claim 8, wherein the motor and the front wheel are coupled directly so that the motor drives the front wheel directly.
9. The leg direction-control mini-tricycle as claimed in claim 1, wherein driven element and driven wheel are realized by a chain with a chain wheel.
10. The leg direction-control mini-tricycle as claimed in claim 1, wherein driven element and the driven wheel are realized by a belt with a belt wheel.
11. The leg direction-control mini-tricycle as claimed in claim 8, wherein a control means is assembled to the electromotive means; the control means is at the pedal and has a pedal moving forward switch, a pedal moving backward switch, and a brake.
12. The leg direction-control mini-tricycle as claimed in claim 1, wherein a moving forward switch, a moving backward switch and a brake are installed on the handles.
13. The leg direction-control mini-tricycle as claimed in claim 1, wherein the number of rear wheels is changeable.
14. The leg direction-control mini-tricycle as claimed in claim 1, wherein the mini-tricycle is driven by an engine.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
obtaining a premolded substrate including a leadframe structure and a molding material, wherein the leadframe structure includes a first conductive portion, a second conductive portion, and an intermediate portion between the first conductive portion and the second conductive portion;
cutting the intermediate portion to electrically isolate the first conductive portion from the second conductive portion;
attaching a semiconductor die to the substrate; and
electrically coupling the first and second conductive portions to the semiconductor die.
2. The method of claim 1 wherein the intermediate portion is formed using an etching process.
3. The method of claim 1 wherein surfaces of the first and second conductive portions are substantially coplanar with an exterior surface of the molding material.
4. The method of claim 1 wherein electrically coupling the first conductive portion and the second conductive portion to the semiconductor die comprises wirebonding the first conductive portion to the semiconductor die and wirebonding the second conductive portion to the semiconductor die.
5. The method of claim 1 wherein cutting comprises using a saw, a laser, or a water jet to cut the intermediate portion.
6. The method of claim 1 further comprising, after attaching the die to the semiconductor substrate, encapsulating the semiconductor die using an encapsulating material, wherein the encapsulating material fills a region between the first conductive portion and the second conductive portion.
7. The method of claim 1 wherein the premolded substrate is in an array of premolded substrates.
8. The method of claim 1 wherein the conductive portions do not extend past the molding material.
9. The method of claim 1 wherein the attached semiconductor die overlaps with at least a portion of the first conductive portion.
10. The method of claim 9 wherein the leadframe structure further comprises a conductive central portion inside of a region defined by a plurality of first conductive portions.
11. A semiconductor die package comprising:
a premolded substrate including a leadframe structure and a molding material, wherein the leadframe structure includes a first conductive portion, a second conductive portion, and a cavity between the first conductive portion and the second conductive portion;
a semiconductor die on the premolded substrate; and
an encapsulating material covering the semiconductor die and filling the cavity between the first conductive portion and the second conductive portion.
12. The semiconductor die package of claim 11 wherein the semiconductor die comprises a power MOSFET.
13. The semiconductor die package of claim 11 wherein the semiconductor die comprises a vertical device.
14. The semiconductor die package of claim 11 wherein the semiconductor die has a first surface distal to the substrate and a second surface proximate to the substrate, wherein the package further includes wirebonds coupling the first surface of the die to the substrate.
15. The semiconductor die package of claim 11 wherein the semiconductor die is directly over an insulated portion of the substrate.
16. The semiconductor die package of claim 11 wherein the semiconductor die package does not have leads extending laterally away from the encapsulating material.
17. The semiconductor die package of claim 11 wherein the cavity was formed by cutting.
18. The semiconductor die package of claim 11 wherein the cavity was formed by cutting using a saw, a laser, or a water jet.
19. The semiconductor die package of claim 11 wherein the attached semiconductor die overlaps with at least a portion of the first conductive portion.
20. The semiconductor die package of claim 11 wherein the leadframe structure further comprises a conductive central portion inside of a region defined by a plurality of first conductive portions.
21. A method comprising:
obtaining a premolded substrate including a first surface and a second surface, wherein the premolded substrate includes a leadframe structure and a molding material, wherein the leadframe structure comprises a pad region, wherein an exterior surface of the pad region and an exterior surface of the molding material are substantially coplanar and coincide with the second surface of the premolded substrate; and
attaching at least two semiconductor dice to the first surface of premolded substrate.
22. The method of claim 21 wherein the leadframe structure includes a plurality of conductive regions, wherein the plurality of conductive regions are at edge regions of the substrate.
23. The method of claim 21 wherein the at least two semiconductor dice are attached using solder.
24. The method of claim 21 wherein the at least two semiconductor dice are attached using an adhesive.
25. The method of claim 21 wherein the leadframe structure includes a die attach region, wherein the die attach region coincides with the first surface of the substrate and at least one of the dice is on the die attach region.
26. The method of claim 21 wherein the leadframe structure comprises copper.
27. The method of claim 21 wherein the substrate does not have leads that extend laterally past the molding material.
28. The method of claim 21 wherein at least one of the semiconductor dice comprises a vertical device.
29. The method of claim 21 wherein at least one of the dice comprises a vertical MOSFET.
30. The method of claim 21 wherein the leadframe structure includes a plurality of conductive regions, wherein the plurality of conductive regions are at edge regions of the substrate, and wherein the method further comprises wirebonding the dice to the conductive regions.
31. A semiconductor die package comprising:
a premolded substrate including a first surface and a second surface, wherein the premolded substrate includes a leadframe structure and a molding material, wherein the leadframe structure comprises a pad region, wherein an exterior surface of the pad region and an exterior surface of the molding material are substantially coplanar and coincide with the second surface of the premolded substrate; and
at least two semiconductor dice coupled to the first surface of premolded substrate.
32. The semiconductor die package of claim 31 wherein the leadframe structure includes a plurality of conductive regions, wherein the plurality of conductive regions are at edge regions of the substrate.
33. The semiconductor die package of claim 31 wherein the at least two semiconductor dice are attached using solder.
34. The semiconductor die package of claim 31 wherein the at least two semiconductor dice are attached to the substrate using an adhesive.
35. The semiconductor die package of claim 31 wherein the leadframe structure includes a die attach region, wherein the die attach region coincides with the first surface of the substrate and at least one of the dice is on the die attach region.
36. The semiconductor die package of claim 31 wherein the leadframe structure comprises copper.
37. The semiconductor die package of claim 21 wherein the substrate does not have leads that extend laterally past the molding material.
38. The semiconductor die package of claim 31 wherein at least one of the semiconductor dice comprises a vertical device.
39. The semiconductor die package of claim 31 wherein at least one of the dice comprises a vertical MOSFET.
40. The semiconductor die package of claim 31 wherein the leadframe structure includes a plurality of conductive regions, wherein the plurality of conductive regions are at edge regions of the substrate, and wherein the method further comprises wirebonding the dice to the conductive regions.
41. A method for forming a forming a semiconductor die package, the method comprising:
forming a substrate, wherein forming a substrate comprises (i) placing a leadframe structure between at least a first molding die and a second molding die, (ii) contacting the leadframe structure with the first and second molding dies, and (iii) forming a molding material around the leadframe structure;
attaching a semiconductor die to the substrate; and
encapsulating the semiconductor die in an encapsulating material.
42. The method of claim 41 wherein the semiconductor die is attached to the substrate using an adhesive.
43. The method of claim 41 wherein the semiconductor die comprises a power MOSFET.
44. The method of claim 41 wherein the formed substrate includes two concave structures on opposite sides of the substrate.
45. The method of claim 41 wherein the molding material has a thickness that is equal to a thickness of the leadframe structure.
46. The method of claim 41 wherein the formed substrate includes one concave structure on one side of the substrate.
47. The method of claim 41 wherein the leadframe structure is in an array of leadframe structures, and wherein the method further comprises after encapsulating:
separating the leadframe structures in the array to form individual die packages.
48. The method of claim 41 wherein the leadframe structure comprises copper.
49. The method of claim 41 further comprising forming wirebonds bonding the semiconductor die to leads in the leadframe structure.
50. The method of claim 41 wherein a semiconductor die package that is formed after encapsulating does not have leads that extend beyond the encapsulating material.
51. A semiconductor die package comprising:
a substrate, wherein forming a substrate comprises a leadframe structure and a molding material, wherein the substrate forms at least one concave structure; and
a semiconductor die on the substrate.
52. The semiconductor die package of claim 51 further comprising an encapsulating material over the semiconductor die.
53. The semiconductor die package of claim 51 further comprising wirebonds formed between the semiconductor die and the leadframe structure in the substrate.
54. The semiconductor die package of claim 51 wherein the substrate has two concave structures that are on opposite sides of the substrate.
55. The semiconductor die package of claim 51 wherein the concave structure is formed by raised walls of the molding material and a surface of the leadframe structure.
56. The semiconductor die package of claim 51 wherein the semiconductor die comprises a power transistor.
57. The semiconductor die package of claim 51 wherein the semiconductor die comprises a power MOSFET.
58. The semiconductor die package of claim 51 wherein the leadframe structure comprises copper.
59. The semiconductor die package of claim 51 wherein the semiconductor die is a first semiconductor die and wherein the semiconductor die package further comprises a second semiconductor die on the substrate.
60. The semiconductor die package of claim 51 further comprising an encapsulating material on the semiconductor die, and wherein leads of the leadframe structure do not extend past the encapsulating material.
61. A method comprising:
obtaining a substrate including a leadframe structure and a molding material, wherein a surface of the molding material and the leadframe structure are substantially coplanar, and wherein the substrate includes a first die attach region and a second die attach region;
attaching a first semiconductor die to the first die attach region; and
attaching a second semiconductor die to the second die attach region.
62. The method of claim 61 wherein the first semiconductor die comprises a driver IC and wherein the second semiconductor die includes a power transistor.
63. The method of claim 61 wherein the method further comprises attaching a third semiconductor die to the substrate.
64. The method of claim 61 wherein the method comprises encapsulating the first and second semiconductor dice using an encapsulating material.
65. The method of claim 61 wherein the leadframe structure includes copper.
66. The method of claim 61 further comprising forming the substrate, wherein forming the substrate includes partially etching the leadframe structure and then molding the molding material around the leadframe structure such that a non-etched surface is substantially coplanar with an exterior surface of the molded molding material.
67. The method of claim 61 further comprising forming the substrate, wherein forming the substrate includes partially etching the leadframe structure;
covering non-etched surfaces of the leadframe structure with tape; and then molding the molding material around the leadframe structure such that a non-etched surface is substantially coplanar with an exterior surface of the molded molding material.
68. The method of claim 61 wherein at least one of the dice comprises a vertical device.
69. The method of claim 61 wherein at least one of the dice comprises a power MOSFET.
70. The method of claim 61 wherein the leadframe structure includes a plurality of leads that extend laterally past a side exterior surface of the molding material in the substrate.
71. A semiconductor die package comprising:
a substrate including a leadframe structure and a molding material, wherein a surface of the molding material and the leadframe structure are substantially coplanar, and wherein the substrate includes a first die attach region and a second die attach region;
a first semiconductor die on the first die attach region; and
a second semiconductor die on the second die attach region.
72. The semiconductor die package of claim 71 wherein the first semiconductor die comprises a driver IC and wherein the second semiconductor die includes a power transistor.
73. The semiconductor die package of claim 71 further comprising a third semiconductor die attached to the substrate.
74. The semiconductor die package of claim 71 further comprising an encapsulating material encapsulating the first and second semiconductor dice.
75. The semiconductor die package of claim 71 wherein the leadframe structure includes copper.
76. The semiconductor die package of claim 71 wherein the substrate includes a partially etched structure and wherein the molding material is disposed around the leadframe structure such that a non-etched surface is substantially coplanar with an exterior surface of the molded molding material.
77. The semiconductor die package of claim 71 wherein the substrate includes a partially etched structure and wherein the molding material is disposed around the leadframe structure such that a non-etched surface is substantially coplanar with an exterior surface of the molded molding material, and wherein the leadframe structure includes copper.
78. The semiconductor die package of claim 71 wherein at least one of the dice comprises a vertical device.
79. The semiconductor die package of claim 71 wherein at least one of the dice comprises a power MOSFET.
80. The semiconductor die package of claim 71 wherein the leadframe structure includes a plurality of leads that extend laterally past a side exterior surface of the molding material in the substrate.
81. A method for making a substrate for a semiconductor die package, the method comprising:
obtaining a first leadframe structure and a second leadframe structure;
attaching the first and second leadframe structure together using an adhesion layer; and
applying a molding material to the first leadframe structure, the second leadframe structure, or the adhesion layer.
82. The method of claim 81 wherein applying the molding material to the first leadframe structure, the second leadframe structure, and the adhesion layer comprises applying the molding material to the first leadframe structure, the second leadframe structure, and the adhesion layer.
83. The method of claim 81 wherein the first leadframe structure is partially etched and the second leadframe structure is partially etched.
84. The method of claim 81 wherein the adhesion layer is in the form of a polymeric film.
85. The method of claim 81 wherein the adhesion layer is in the form of a polyimide film.
86. The method of claim 81 wherein the first leadframe structure and the second leadframe structure are symmetrically disposed at opposite sides of the adhesion layer.
87. The method of claim 81 wherein the first and second leadframe structures include cavities, and wherein the cavities in the first and second leadframe structures are filled with the molding material, and where edges of the first and second leadframe are coated with the molding material.
88. The method of claim 81 wherein the molding material in the substrate has an exterior surface that is substantially coplanar with an exterior surface of the first leadframe structure or the second leadframe structure.
89. The method of claim 81, wherein the molding material in the substrate has exterior surfaces, which are substantially coplanar with exterior surfaces of the first leadframe structure and the second leadframe structure.
90. The method of claim 81 wherein the first and second leadframe structures comprise copper.
91. A substrate for a semiconductor die package, the substrate comprising:
a first leadframe structure;
a second leadframe structure; and
an adhesion layer adhering the first and second leadframe structures together; and
a molding material on the first leadframe structure, the second leadframe structure, or the adhesion layer.
92. The substrate of claim 91 wherein the molding material is on the first leadframe structure, the second leadframe structure, and the adhesion layer.
93. The substrate of claim 91 wherein the first leadframe structure is partially etched and the second leadframe structure is partially etched.
94. The substrate of claim 91 wherein the adhesion layer is in the form of a polymeric film.
95. The substrate of claim 91 wherein the first and second leadframe structures comprise copper.
96. The substrate of claim 91 wherein the adhesion layer is in the form of a polyimide film.
97. The substrate of claim 91 wherein the molding material in the substrate has an exterior surface that is substantially coplanar with an exterior surface of the first leadframe structure or the second leadframe structure.
98. The substrate of claim 91 wherein the first and second leadframe structures include cavities, and wherein the cavities in the first and second leadframe structures are filled with the molding material, and where edges of the first and second leadframe are coated with the molding material.
99. The substrate of claim 91 wherein the molding material in the substrate has exterior surfaces, which are substantially coplanar with exterior surfaces of the first leadframe structure and the second leadframe structure.
100. The substrate of claim 91 wherein the first leadframe structure and the second leadframe structure are symmetrically disposed at opposite sides of the adhesion layer.
101. A method of forming a semiconductor die package comprising:
obtaining a premolded substrate comprising a leadframe structure and a molding material, wherein an exterior surface of the leadframe structure and an exterior surface of the molding material are substantially coplanar;
attaching the substrate to a frame structure including leads; and
attaching a die to the substrate.
102. The method of claim 101 wherein the leadframe structure comprises copper.
103. The method of claim 101 further comprising forming a molding material around the attached substrate, and separating the leads from the frame structure.
104. The method of claim 101 further comprising attaching a plurality of dice to the substrate before or after attaching the substrate to the frame structure.
105. The method of claim 101 wherein after the substrate is attached to the frame structure, the substrate is downset with respect to a major portion of the frame structure.
106. A semiconductor die package comprising:
a premolded substrate comprising a leadframe structure and a molding material, wherein an exterior surface of the leadframe structure and an exterior surface of the molding material are substantially coplanar; and
a semiconductor die on the premolded substrate;
leads attached to the premolded substrate, wherein the leads were separately formed from the premolded substrate.
107. The semiconductor die package of claim 106 wherein the leadframe structure comprises copper.
108. The semiconductor die package of claim 106 wherein the molding material has opposite surfaces that are substantially coplanar with opposite surfaces of the leadframe structure.
109. The semiconductor die package of claim 106 wherein the leads are attached to the premolded substrate through solder or welds.
110. The semiconductor die package of claim 106 wherein the semiconductor die comprises a vertical device.
111. A method comprising:
obtaining a substrate comprising a conductive die attach surface;
attaching a high side transistor including a high side transistor input to the substrate, wherein the high side transistor input is coupled to the conductive die attach surface; and
attaching a low side transistor including a low side transistor output to the substrate, wherein the low side transistor input is coupled to the conductive die attach surface.
112. The method of claim 111 further comprising:
forming an encapsulating material formed around the high side transistor and the low side transistor.
113. The method of claim 111 wherein the high side transistor is a high side MOSFET and the high side transistor input is a high side transistor source connection.
114. The method of claim 111 wherein the low side transistor is a low side MOSFET and the low side transistor output is a low side transistor drain connection.
115. The method of claim 111 wherein the high side transistor is in a first die and the low side transistor is in the second die.
116. The method of claim 111 further comprising mounting a controller chip mounted on the substrate.
117. The method of claim 111 wherein the substrate comprises a molding material that has an exterior surface that is substantially coplanar with the conductive die attach surface.
118. The method of claim 111 wherein the conductive die attach surface is part of a leadframe.
119. The method of claim 111 wherein the high side transistor has a high side transistor output, wherein the high side transistor output is distal to the conductive die attach surface and the high side transistor input is proximate the conductive die attach surface and wherein the package further comprises a clip or wirebond coupling the high side transistor output to external leads, and wherein the high and low side transistors are both power MOSFETs.
120. The method of claim 111 further comprising attaching a controller chip to the substrate and wherein the conductive die attach surface is part of a leadframe structure.
121. A semiconductor device package comprising:
a substrate comprising a conductive die attach surface;
a high side transistor including a high side transistor input, wherein the high side transistor input is coupled to the conductive die attach surface; and
a low side transistor including a low side transistor output, wherein the low side transistor input is coupled to the conductive die attach surface.
122. The semiconductor die package of claim 121 further comprising:
an encapsulating material formed around the high side transistor and the low side transistor.
123. The semiconductor die package of claim 121 wherein the high side transistor is a high side MOSFET and the high side transistor input is a high side transistor source connection.
124. The semiconductor die package of claim 121 wherein the low side transistor is a low side MOSFET and the low side transistor output is a low side transistor drain connection.
125. The semiconductor die package of claim 121 wherein the high side transistor is a high side MOSFET and the low side transistor is a low side MOSFET and the low side transistor output is a low side transistor drain connection.
126. The semiconductor die package of claim 121 further comprising a controller chip mounted on the substrate.
127. The semiconductor die package of claim 121 wherein the conductive die attach surface is part of a leadframe.
128. The semiconductor die package of claim 121 wherein the substrate comprises a molding material that has an exterior surface that is substantially coplanar with the conductive die attach surface.
129. The semiconductor die package of claim 121 wherein the high side transistor has a high side transistor output, wherein the high side transistor output is distal to the conductive die attach surface and the high side transistor input is proximate the conductive die attach surface and wherein the package further comprises a clip or wirebond coupling the high side transistor output to external leads.
130. The semiconductor die package of claim 121 wherein the high side transistor has a high side transistor output, wherein the high side transistor output is distal to the conductive die attach surface and the high side transistor input is proximate the conductive die attach surface and wherein the package further comprises a clip or wirebond coupling the high side transistor output to external leads, and wherein the high and low side transistors are both power MOSFETs.
131. A method for forming a semiconductor die package comprising:
forming a substrate comprising a conductive surface and a recess;
filling the recess with a molding material;
mounting a first chip on the molding material; and
mounting a die on the conductive surface of the substrate.
132. The method of claim 131 wherein the chip is a control chip and the die is a MOSFET die.
133. The method of claim 131 wherein the die is a first die and wherein the package comprises a second die, wherein the second die is also mounted on the conductive surface of the substrate.
134. The method of claim 133 wherein the first die is a first MOSFET die and the second die is a second MOSFET die.
135. The method of claim 134 wherein the first MOSFET die is a high side MOSFET die and the second MOSFET die is a low side MOSFET die.