1. A variable evaporator control refrigerated compressed gas dryer comprising:
a. an evaporator heat exchanger having a first flow path for compressed gas at a first temperature;
b. said evaporator heat exchanger having a second flow path for a refrigerant at a second temperature which is lower than said first temperature to cool said compressed gas to a third temperature;
c. a compressor to circulate said refrigerant at a predetermined pressure, said predetermined pressure having a correlation to said second temperature;
d. a temperature sensor to sense said third temperature at an outlet of said first flow path, wherein said temperature sensor positioned at a single location to sense a fourth temperature wherein said fourth temperature is representative of said third temperature when a compressed gas load is above a certain level, and representative of said second temperature when said compressed gas load is below said certain level;
e. a valve intermediate said second flow path and a source of refrigerant, said valve controllable to admit refrigerant into circulation to adjust said predetermined pressure; and
f. a controller connected to receive feedback from said temperature sensor indicative of said third temperature, said controller controlling said valve to adjust said predetermined pressure and thus adjust said second temperature to generally maintain said third temperature at a desired value, wherein said controller connected to receive feedback from said temperature sensor indicative of said fourth temperature to control said valve to adjust said predetermined pressure and thus said second temperature such that said fourth temperature is generally maintained at said desired value; and
g. a smooth tube evaporator heat exchanger.
2. The compressed gas dryer of claim 1 wherein said smooth tube evaporator heat exchanger further comprises:
a. an outer cover;
b. a plurality of smooth tubes enclosed within said outer cover, said first flow path being at least partially through said plurality of smooth tubes;
c. said second flow path being within said outer cover and communicating with an exterior of said plurality of smooth tubes;
d. a tube sheet dividing a portion of said evaporator heat exchanger, said second flow path communicating on a first side of said tube sheet;
e. each of said plurality of smooth tubes having an end extending through said tube sheet to a second side thereof which is not in communication with said second flow path; and
f. said single point temperature sensor being disposed in contact with said end of at least one of said plurality of smooth tubes which extends through said tube sheet.
3. The compressed gas dryer of claim 2 further comprising said end in contact with said single point temperature sensor having an extended length portion, and said single point temperature sensor disposed in contact with said extended length portions.
4. A variable evaporator control system comprising:
a. an evaporator heat exchanger having a first flow path for a gas at a first temperature and a second flow path for circulation of a refrigerant at a second temperature which is lower than said first temperature to cool said gas to a third temperature;
b. a compressor to circulate said refrigerant;
c. a temperature sensor positioned in said evaporator heat exchanger at a single location to sense a fourth temperature which is representative of said third temperature when a gas load is above a certain level, and representative of said second temperature when said gas load is below said certain level; and
d. a controller connected to receive feedback from said temperature sensor indicative of said fourth temperature to control said second temperature to generally maintain said fourth temperature at a desired value.
5. The variable evaporator control system of claim 4 further comprising:
a. compressor to circulate said refrigerant at a predetermined pressure, said second temperature having a correlation to said predetermined pressure; and
b. a valve positioned intermediate said second flow path and a source of refrigerant, said valve controllable by said controller to adjust admission of said refrigerant into circulation to adjust said predetermined pressure and thus adjust said second temperature to generally maintain said fourth temperature at said desired value.
6. A compressed gas dryer having a heat exchanger with a first flow path for a compressed gas and a second flow path for a refrigerant to cool said compressed gas, the compressed gas dryer comprising:
a. a temperature sensor to sense a temperature of said compressed gas at an outlet of said first flow path;
b. a controller connected to receive feed back from said temperature sensor indicative of said temperature of said compressed gas at said outlet of said first flow path, said controller controlling a temperature of said refrigerant at an inlet of said second flow path to generally maintain said temperature of said compressed gas at said outlet of said first flow path at a desired value;
c. said temperature sensor of said compressed gas at said outlet of said first flow path being positioned in said heat exchanger at a single location;
d. a temperature sensed at said single location being representative of said temperature of said compressed gas at said outlet of said first flow path when a compressed gas load is above a certain level; and
e. said temperature sensed at said single location being representative of said temperature of said refrigerant at said second flow when said compressed gas load is below said certain level.
7. The compressed gas dryer of claim 6 further comprising:
said controller controlling said temperature of said refrigerant at said inlet of said second flow path to generally maintaining said temperature sensed at said single location at said desired value.
8. The compressed gas dryer of claim 7 wherein said desired value further comprises a value above 32 degrees Fahrenheit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A pulse width modulation (PWM) regulator integrated circuit (IC), for controlling a duty cycle of at least one switch to convert an input voltage signal into an output voltage, comprising:
a pin, for receiving an input signal different from the input voltage signal, wherein the input signal has a lasting time substantially the same as a time of the input voltage signal situated at a high level, but the input signal has a waveform different from that of the input voltage signal;
a conversion unit, coupled to the pin, for converting the input signal into a square wave signal; and
a PWM controller, for generating at least one PWM drive signal according to the square wave signal to control a duty cycle of the switch.
2. The PWM regulator IC of claim 1, wherein the pin is a ramp signal (RAMP) pin and the input signal is a ramp signal, the pin is coupled to an external conversion unit, which is provided for converting the input voltage signal into a first current signal to charge a capacitor with a potential stored therein corresponding to the ramp signal, and the PWM regulator IC further comprises a current source and a charging switch, connected in series with the capacitor, when the potential stored in the capacitor exceeds a first predetermined voltage, the charging switch is conducted to have the current source charging the capacitor, and when the input voltage signal is turned to a low level, the external conversion circuit constitutes a discharge path to discharge the capacitor quickly to drop the potential stored in the capacitor.
3. The PWM regulator IC of claim 2, wherein the current source charges the capacitor with a charging speed much faster than that for the first current signal to charge the capacitor, and a discharging speed of the capacitor through the discharge path is faster than the charging speed for the current source to charge the capacitor.
4. The PWM regulator IC of claim 3, wherein when the potential of the capacitor rises above a second predetermined voltage, the current source stops charging the capacitor.
5. The PWM regulator IC of claim 3, wherein when the potential of the capacitor drops below a second predetermined voltage, the current source stops charging the capacitor.
6. The PWM regulator IC of claim 2, wherein the conversion unit is a comparator.
7. The PWM regulator IC of claim 2, further comprising a feedback compare circuit, for generating a comparison signal to be inputted into the PWM controller according to the ramp signal and a feedback signal, and the PWM controller generates the PWM drive signal according to the square wave signal and the comparison signal.
8. The PWM regulator IC of claim 1, wherein the PWM controller generates two PWM drive signals for controlling duty cycles of a high voltage switch and a low voltage switch respectively, the pin is a boost (BST) pin, and the input signal is a bootstrap high voltage signal for providing a voltage required for driving the high voltage switch, and the boost pin is coupled to a bootstrap capacitor, which is coupled between a power supply terminal and the low voltage switch and the bootstrap high voltage signal is generated at a high voltage side of the bootstrap capacitor.
9. The PWM regulator IC of claim 8, wherein the conversion unit is a hysteresis comparator with a first voltage reference level and a second voltage reference level, the hysteresis comparator compares a voltage value of a rising edge of the input signal with the first voltage reference level and compares a voltage value of a falling edge of the input signal with the second voltage reference level, and the first voltage reference level is lower than the second voltage reference level.
10. A pulse width modulation (PWM) synchronous buck DC-to-DC converter circuit, for receiving an input voltage signal and generating an output voltage, comprising:
at least one switch, a level of the output voltage being adjusted by changing a duty cycle of the switch; and
a PWM regulator IC, comprising:
a pin, for receiving an input signal different from the input voltage signal, wherein a lasting time of the input signal is substantially the same as a time of the input voltage signal situated at a high level, but the input signal has a waveform different from that of the input voltage signal;
a conversion unit, coupled to the pin, for converting the input signal into a square wave signal; and
a PWM controller, for generating at least one PWM drive signal according to the square wave signal to control a duty cycle of the switch.
11. The PWM synchronous buck DC-to-DC converter circuit of claim 10, wherein the pin is a ramp signal pin and the input signal is a ramp signal, and the PWM synchronous buck DC-to-DC converter circuit further comprises an external conversion circuit coupled to the pin for receiving the input voltage signal and converting the input voltage signal into a first current signal to charge a capacitor, and a potential stored in the capacitor corresponds to the ramp signal.
12. The PWM synchronous buck DC-to-DC converter circuit of claim 11, wherein the capacitor is externally coupled to the pin.
13. The PWM synchronous buck DC-to-DC converter circuit of claim 11, wherein the capacitor is located in the pulse width modulation regulator IC.
14. The PWM synchronous buck DC-to-DC converter circuit of claim 11, wherein the PWM regulator IC includes a current source and a charging switch, connected in series with the capacitor, such that when the potential stored in the capacitor exceeds a first predetermined voltage, the charging switch is conducted to have the current source charging the capacitor, and when the input voltage signal is turned to a low level, the external conversion circuit constitutes a discharge path to discharge the capacitor quickly to drop the potential stored in the capacitor, and a charging speed for the current source to charge the capacitor is much faster than a charging speed for the first current signal to charge the capacitor, and a discharging speed of the capacitor through the external conversion circuit is much faster than the charging speed for the current source to charge the capacitor.
15. The PWM synchronous buck DC-to-DC converter circuit of claim 14, wherein when the potential stored in the capacitor rises above a second predetermined voltage, the current source stops charging the capacitor.
16. The PWM synchronous buck DC-to-DC converter circuit of claim 14, wherein when the potential stored in the capacitor drops below a second predetermined voltage, the current source stops charging the capacitor.
17. The PWM synchronous buck DC-to-DC converter circuit of claim 11, wherein the PWM regulator IC includes a feedback compare circuit, for generating and inputting a comparison signal to the PWM controller according to the ramp signal and a feedback signal, and the PWM controller generates the PWM drive signal according to the square wave signal and the comparison signal.
18. The PWM synchronous buck DC-to-DC converter circuit of claim 10, wherein at least two switches including a high voltage switch and a low voltage switch connected in series between an input terminal for inputting the input voltage signal and a ground terminal are used, the PWM controller is provided for generating two PWM drive signals to control duty cycles of the two switches, the pin is a boost (BST) pin, and the input signal is a bootstrap high voltage signal for supplying a voltage to drive the high voltage switch, and the boost pin is coupled to a bootstrap capacitor, which is coupled between a power supply terminal and the low voltage switch, and the bootstrap high voltage signal is generated at a high voltage side of the bootstrap capacitor.
19. The PWM synchronous buck DC-to-DC converter circuit of claim 18, wherein the conversion unit is a hysteresis comparator with a first voltage reference level and a second voltage reference level, the hysteresis comparator compares a voltage value of a rising edge of the input signal with the first voltage reference level and compares a voltage value of a falling edge of the input signal with the second voltage reference level, and the first voltage reference level is lower than the second voltage reference level.
20. A PWM synchronous buck DC-to-DC converter circuit, comprising:
a wave mixer, for receiving an input voltage signal and a feedback signal, and mixing the input voltage signal and the feedback signal to form a mixed wave signal, wherein the input voltage signal has a frequency much higher than that of the feedback signal; and
a PWM regulator IC, including:
an input signal pin, for receiving the mixed wave signal;
a comparator, for comparing the mixed wave signal with a predetermined voltage level to generate a first recovered signal, which has a duty cycle equal to that of the input voltage signal;
an error amplifier, for filtering out a high frequency portion of the mixed wave signal to generate a second recovered signal corresponding to the feedback signal; and
a PWM controller, for comparing the second recovered signal with a ramp signal to generate a comparison signal, and generating a PWM drive signal according to the comparison signal and the first recovered signal.