1. A device for use with a first apparatus that is connectable to a second apparatus, the first apparatus containing a memory and a first processor operating a stack of protocol processing layers that create a context for communication, the context including a media access control (MAC) layer address, an Internet Protocol (IP) address and Transmission Control Protocol (TCP) state information, the device comprising:
a communication processing mechanism connected to the first processor, said communication processing mechanism containing a second processor running instructions to process a message packet such that the context is employed to transfer data contained in said packet to the first apparatus memory and the TCP state information is updated by said second processor.
2. The device of claim 1, wherein said communication processing mechanism includes a receive sequencer with directions to classify said packet, wherein said packet contains control information corresponding to the stack of protocol layers.
3. The device of claim 1, wherein said communication processing mechanism includes a receive sequencer with directions to generate a summary of a second message packet received from the network, said second packet containing control information corresponding to the stack of protocol layers, and said instructions including an instruction to compare said summary with said context.
4. The device of claim 1, wherein said instructions include a first instruction to create a header corresponding to said context and having control information corresponding to several of the protocol processing layers, and said instructions include a second instruction to prepend said header to second data for transmission of a second packet.
5. The device of claim 1, wherein said communication processing mechanism has a direct memory access unit to send, based upon said context, said data from said communication processing mechanism to the first apparatus memory, without a header accompanying said data.
6. The device of claim 1, wherein said context includes a receive window of space in the memory that is available to store application data, and said communication processing mechanism advertises said receive window.
7. The device of claim 1, wherein said context includes TCP ports of said first and said second apparatuses.
8. The device of claim 1, wherein said context is transferred from said first processor to said communication processing mechanism.
9. A device for use with a first apparatus that can communicate with a second apparatus, the first apparatus containing a first processor operating a stack of protocol processing layers that create a Transmission Control Protocol (TCP) connection for communication between a first application on the first apparatus and a second application on the second apparatus, the device comprising:
a receive mechanism having logic to classify a message packet received from the second apparatus by the device, said message packet containing data and a header with control information corresponding to several of said protocol layers, said logic including directions to create a descriptor of said packet, and
a second processor coupled to said receive mechanism and to the first apparatus, having instructions to compare said descriptor with the TCP connection and to choose whether to send said message packet to the stack for protocol processing or to update said TCP connection and send said data directly to the first application without processing said message packet by the stack.
10. The device of claim 9, wherein said receive mechanism includes a sequencer.
11. The device of claim 9, further comprising a queue manager containing logic circuits to provide information for said second processor.
12. The device of claim 9, wherein said receive mechanism and said second processor process a plurality of message packets to send data from each of said packets to said destination without an interrupt.
13. The device of claim 9, wherein the connection is one of a plurality of TCP connections maintained by the device, and a hash that indicates each said connection is stored in a memory of the device.
14. The device of claim 13, further comprising a least recently used register (LRU) for determining which of said connections are stored in said memory.
15. The device of claim 9, wherein said receive mechanism has a sequence of hardware logic units for processing said header.
16. The device of claim 9, further comprising a direct memory access (DMA) controller for sending, based upon said connection, said data to said first application without said header.
17. The device of claim 9, further comprising directions for said second processor to transmit a second message packet from the first apparatus to the second apparatus without employing the stack, including directions to create a header corresponding to said connection as part of said second message packet.
18. A method for communication between a first device and a second device, the method comprising:
establishing, by a processor of the first device, a Transmission Control Protocol (TCP) connection corresponding to an application running on the first device;
transferring Media Access Control (MAC) and Internet Protocol (IP) addresses corresponding to the TCP connection from the processor to an interface for the first device, and transferring control of the TCP connection from the processor to the interface;
receiving a message packet by the interface, including parsing a header of the packet with hardware of the interface and determining that the packet corresponds to the TCP connection;
sending to the application, by the interface, data of the packet without the header; and
updating the TCP connection, by the interface, to reflect receipt of the packet.
19. The method of claim 18, further comprising creating, by the interface, an acknowledgement that corresponds to the TCP connection and indicates that the data was received by the application.
20. The method of claim 18, further comprising advertising to the second device, by the interface, a receive window of space in memory that corresponds to the TCP connection and is available to store additional data for the application.
21. The method of claim 18, further comprising transmitting, by the interface, a second message packet, including prepending second data from the application with a second header corresponding to the TCP connection.
22. The method of claim 18, wherein determining that the packet corresponds to the TCP connection includes comparing, with the hardware of the interface, TCP ports of the packet with those of the TCP connection.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit comprising:
a first contact area from a first logic cell; and
a second contact area from a second logic cell comprising a non-zero, non-opposing effect with respect to the first contact area, wherein the first contact area and the second contact area comprise a first distance, wherein when the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.
2. The integrated circuit of claim 1, wherein when the first distance is equal to or greater than the predetermined threshold, a filter cell is inserted between the first contact area and the second contact area to decouple the first contact area and the second contact area, and wherein the first contact area is placed along the first R-line and the second contact area is placed along a second R-line.
3. The integrated circuit of claim 2, wherein the filter cell is placed at least partially along the second R-line.
4. The integrated circuit of claim 3, wherein the filter cell comprises a first circuit path comprising one or more contact areas placed along the first R-line and a second circuit path placed along the second R-line.
5. The integrated circuit of claim 2, wherein the filter cell comprises:
a first p-type MOSFET comprising a source coupled to a power net, a drain, and a gate coupled to an input;
a second p-type MOSFET comprising a source coupled to the drain of the first p-type MOSFET, a drain coupled to an inverse output, and a gate;
a third p-type MOSFET comprising a source coupled to the power net, a drain, and a gate coupled to an inverse input;
a fourth p-type MOSFET comprising a source coupled to the drain of the third p-type MOSFET, a drain coupled to an output, and a gate;
a first n-type MOSFET comprising a source coupled to a ground net, a drain, and a gate coupled to the input;
a second n-type MOSFET comprising a source coupled to the drain of the first n-type MOSFET, a drain coupled to the inverse output, and a gate;
a third n-type MOSFET comprising a source coupled to the ground net, a drain, and a gate coupled to the inverse input; and
a fourth n-type MOSFET comprising a source coupled to the drain of the third n-type MOSFET, a drain coupled to the output, and a gate,
6. The integrated circuit of claim 5, wherein the gate of the second p-type MOSFET is coupled to the drain of the third n-type MOSFET, the gate of the second n-type MOSFET is coupled to the drain of the third p-type MOSFET, the gate of the fourth p-type MOSFET is coupled to the drain of the first n-type MOSFET, and the gate of the fourth n-type MOSFET is coupled to the drain of the first p-type MOSFET.
7. The integrated circuit of claim 5, comprising: a dual redundant inverter cell coupled to the input and the inverse input, wherein the dual redundant inverter cell comprises a first output comprising the complement of the input and a second output comprising the complement of the inverse input, wherein the gate of the second p-type MOSFET and the gate of the second n-type MOSFET are coupled to the second output and the gate of the fourth p-type MOSFET and the gate of the fourth n-type MOSFET are coupled to the first output.
8. The integrated circuit of claim 5, comprising a first node coupled to the output and a second node coupled to the inverse output, wherein the first node and the second node comprise a plurality of contact areas, and wherein the plurality of contact areas are placed along the same R-line of a circuit, and wherein the contact areas are placed such that (n-Q, n-Qi, p-Qi, p-Q)
9. The integrated circuit of claim 2, comprising:
an output for a first input, a second input, and a third input;
an inverse output for a first inverse input, a second inverse input, and a third inverse input, wherein the output logic and the inverse output logic comprise:
a first p-type MOSFET comprising a source coupled to a power net of a circuit, a drain coupled to the output, and a gate coupled to the first input;
a second p-type MOSFET comprising a source coupled to the power net, a drain coupled to the output, and a gate coupled to the second input;
a third p-type MOSFET comprising a source coupled to the power net, a drain coupled to the output, and a gate coupled to the third input;
a fourth p-type MOSFET comprising a source coupled to the power net, a drain, and a gate coupled to the first inverse input;
a fifth p-type MOSFET comprising a source coupled to the drain of the fourth p-type MOSFET, a drain, and a gate coupled to the second inverse input; and
a sixth p-type MOSFET comprising a source coupled to the drain of the fifth p-type MOSFET, a drain coupled to the inverse output, and a gate coupled to the third inverse input.
10. The integrated circuit of claim 9, wherein the output logic and the inverse output logic comprises:
a first n-type MOSFET comprising a source coupled to a ground net of the circuit, a drain, and a gate coupled to the first input;
a second n-type MOSFET comprising a source coupled to the drain of the first n-type MOSFET, a drain, and a gate coupled to the second input;
a third n-type MOSFET comprising a source coupled to the drain of the second n-type MOSFET, a drain coupled to the output Q, and a gate coupled to the third input;
a fourth n-type MOSFET comprising a source coupled to the ground net, a drain coupled to the output Qi, and a gate coupled to the first inverse input;
a fifth n-type MOSFET comprising a source coupled to the ground net, a drain coupled to the output Qi, and a gate coupled to the second inverse input;
a sixth n-type MOSFET comprising a source coupled to the ground net, a drain coupled to the output Qi, and a gate coupled to the third inverse input.
11. An integrated circuit cell comprising:
a first p-type MOSFET comprising a source coupled to a power net, a drain, and a gate coupled to an input;
a second p-type MOSFET comprising a source coupled to the drain of the first p-type MOSFET, a drain coupled to an inverse output, and a gate;
a third p-type MOSFET comprising a source coupled to the power net, a drain, and a gate coupled to an inverse input;
a fourth p-type MOSFET comprising a source coupled to the drain of the third p-type MOSFET, a drain coupled to an output, and a gate;
a first n-type MOSFET comprising a source coupled to a ground net, a drain, and a gate coupled to the input;
a second n-type MOSFET comprising a source coupled to the drain of the first n-type MOSFET, a drain coupled to the inverse output, and a gate;
a third n-type MOSFET comprising a source coupled to the ground net, a drain, and a gate coupled to the inverse input; and
a fourth n-type MOSFET comprising a source coupled to the drain of the third n-type MOSFET, a drain coupled to the output, and a gate.
12. The integrated circuit cell of claim 11, wherein the gate of the second p-type MOSFET is coupled to the drain of the third n-type MOSFET, the gate of the second n-type MOSFET is coupled to the drain of the third p-type MOSFET, the gate of the fourth p-type MOSFET is coupled to the drain of the first n-type MOSFET, and the gate of the fourth n-type MOSFET is coupled to the drain of the first p-type MOSFET.
13. The integrated circuit cell of claim 11, comprising: a dual redundant inverter cell coupled to the input and the inverse input, wherein the dual redundant inverter cell comprises a first output comprising the complement of the input and a second output comprising the complement of the inverse input, wherein the gate of the second p-type MOSFET and the gate of the second n-type MOSFET are coupled to the second output and the gate of the fourth p-type MOSFET and the gate of the fourth n-type MOSFET are coupled to the first output.
14. The integrated circuit filter cell of claim 11, comprising a first node coupled to the output and a second node coupled to the inverse output, wherein the first node and the second node comprise a plurality of contact areas, and wherein the plurality of contact areas are placed along the same R-line of a circuit, and wherein the contact areas are placed such that each contact area has an opposing effect with respect to a preceding and a following contact.
15. The integrated circuit cell of claim 14, wherein the plurality of contacts are placed in an order comprising n-Q, n-Qi, p-Qi, p-Q, wherein a prefix n indicates a drain or source of an n-type MOSFET and a p prefix indicates a drain or source of a p-type MOSFET, and wherein Q indicates the first output and Qi indicates the inverse output.
16. The integrated circuit cell of claim 14, wherein the plurality of contacts are placed in an order comprising n-Q, p-Q, p-Qi, n-Qi, wherein a prefix n indicates a drain or source of an n-type MOSFET and a p prefix indicates a drain or source of a p-type MOSFET, and wherein Q indicates the first output and Qi indicates the inverse output.
17. An integrated circuit comprising:
a first p-type MOSFET comprising a source coupled to a power net of a circuit, a drain coupled to the output, and a gate coupled to the first input;
a second p-type MOSFET comprising a source coupled to the power net, a drain coupled to the output, and a gate coupled to the second input;
a third p-type MOSFET comprising a source coupled to the power net, a drain coupled to the output, and a gate coupled to the third input;
a fourth p-type MOSFET comprising a source coupled to the power net, a drain, and a gate coupled to the first inverse input;
a fifth p-type MOSFET comprising a source coupled to the drain of the fourth p-type MOSFET, a drain, and a gate coupled to the second inverse input; and
a sixth p-type MOSFET comprising a source coupled to the drain of the fifth p-type MOSFET, a drain coupled to the inverse output, and a gate coupled to the third inverse input.
18. The integrated circuit of claim 17, comprising
a first n-type MOSFET comprising a source coupled to a ground net of the circuit, a drain, and a gate coupled to the first input;
a second n-type MOSFET comprising a source coupled to the drain of the first n-type MOSFET, a drain, and a gate coupled to the second input;
a third n-type MOSFET comprising a source coupled to the drain of the second n-type MOSFET, a drain coupled to the output Q, and a gate coupled to the third input;
a fourth n-type MOSFET comprising a source coupled to the ground net, a drain coupled to the output Qi, and a gate coupled to the first inverse input;
a fifth n-type MOSFET comprising a source coupled to the ground net, a drain coupled to the output Qi, and a gate coupled to the second inverse input;
a sixth n-type MOSFET comprising a source coupled to the ground net, a drain coupled to the output Qi, and a gate coupled to the third inverse input,
19. The integrated circuit of claim 18, comprising a first node coupled to the output Q and a second node coupled to the inverse output Qi, wherein the first node and the second node comprise a plurality of contact areas, and wherein the plurality of contact areas are placed along a first R-line of a circuit, and wherein the contact areas are placed such that each contact area has an opposing effect with respect to a preceding and a following contact.
20. The integrated circuit of claim 19, wherein the plurality of contacts are placed in an order comprising n-Q, n-Qi, p-Qi, p-Q, wherein a prefix n indicates a drain or source of an n-type MOSFET and a p prefix indicates a drain or source of a p-type MOSFET, and wherein Q indicates the first output and Qi indicates the inverse output.
21. The integrated circuit of claim 19, wherein the plurality of contacts are placed in an order comprising n-Q, p-Q, p-Qi, n-Qi, wherein a prefix n indicates a drain or source of an n-type MOSFET and a p prefix indicates a drain or source of a p-type MOSFET, and wherein Q indicates the first output and Qi indicates the inverse output.