1. A programmable logic array (PLA) comprising:
a first plurality of nanoscale wires forming PLA inputs; and
a restoring inverting arrangement connected with the PLA inputs, comprising a second plurality of nanoscale wires, the restoring inverting arrangement restoring signals on the PLA inputs and inverting the signals on the PLA inputs.
2. The PLA of claim 1, further comprising:
a restoring non-inverting arrangement connected with the PLA inputs, comprising a third plurality of nanoscale wires, the restoring non-inverting arrangement restoring the signals on the PLA inputs without inverting the signals on the PLA inputs.
3. The PLA of claim 1, further comprising:
a fourth plurality of nanoscale wires crossing the second plurality of nanoscale wires.
4. The PLA of claim 2, further comprising:
a fourth plurality of nanoscale wires crossing the second plurality of nanoscale wires and the third plurality of nanoscale wires.
5. The PLA of claim 3, further comprising:
programmable ON-OFF devices associated with crossings between the second and fourth plurality of nanoscale wires.
6. The PLA of claim 4, further comprising:
programmable ON-OFF devices associated with crossings between the second and fourth plurality of nanoscale wires and crossings between the third and fourth plurality of nanoscale wires.
7. The PLA of claim 5, wherein the ON-OFF devices are diodes.
8. The PLA of claim 6, wherein the ON-OFF devices are diodes.
9. The PLA of claim 1, wherein one or more nanoscale wires of the second plurality of nanoscale wires comprise controllable regions.
10. The PLA of claim 1, wherein the nanoscale wires of the second plurality of nanoscale wires are assembled stochastically.
11. The PLA of claim 2 wherein one or more nanoscale wires of the second and third plurality of nanoscale wires comprise controllable regions.
12. The PLA of claim 11, wherein the nanoscale wires of the second and third plurality of nanoscale wires are assembled stochastically.
13. The PLA of claim 9 wherein the controllable regions, in conjunction with a plurality of voltages, invert the signals on the PLA inputs along the nanoscale wires of the second plurality of nanoscale wires.
14. The PLA of claim 11 wherein the controllable regions, in conjunction with a plurality of voltages, invert or non-invert the signals on the PLA inputs along the nanoscale wires of the second and third plurality of nanoscale wires, respectively.
15. The PLA of claim 9, wherein the controllable regions are distributed along a portion of the nanoscale wires of the second plurality of nanoscale wires.
16. The PLA of claim 10, wherein the controllable regions are distributed along a portion of the nanoscale wires of the second and third plurality of nanoscale wires.
17. The PLA of claim 1, further comprising:
a plurality of ohmic contacts connected with the PLA inputs, allowing the PLA inputs to be selected.
18. The PLA of claim 17 wherein the ohmic contacts are nanoscale ohmic contacts.
19. The PLA of claim 17 wherein the ohmic contacts are lithographic ohmic contacts.
20. The PLA of claim 17, wherein the PLA inputs are selectable through the ohmic contacts by means of controllable regions located along portions of nanoscale wires of the first plurality of nanoscale wires.
21. The PLA of claim 17, wherein the PLA inputs are independently selectable through the ohmic contacts by means of controllable regions located along portions of nanoscale wires of the first plurality of nanoscale wires.
22. The PLA of claim 1, further comprising:
one or more field-effect junctions connected with the first plurality of nanoscale wires, allowing the first plurality of nanoscale wires to be controlled.
23. The PLA of claim 3, further comprising:
one or more field-effect junctions connected with the first plurality of nanoscale wires, allowing the first plurality of nanoscale wires to be controlled; and
one or more field-effect junctions connected with the fourth plurality of nanoscale wires, allowing the fourth plurality of nanoscale wires to be controlled.
24. The PLA of claim 23, further comprising:
one or more field-effect junctions connected with the second plurality of nanoscale wires, allowing the second plurality of nanoscale wires to be controlled.
25. The PLA of claim 4, further comprising:
a first plurality of programmable ON-OFF devices associated with crossings between the second and fourth plurality of nanoscale wires;
a second plurality of programmable ON-OFF devices associated with crossings between the third and fourth plurality of nanoscale wires;
one or more field-effect junctions connected with the first plurality of nanoscale wires, allowing the first plurality of nanoscale wires to be controlled;
one or more field-effect junctions connected with the second plurality of nanoscale wires, allowing the second plurality of nanoscale wires to be controlled;
one or more field-effect junctions connected with the third plurality of nanoscale wires, allowing the third plurality of nanoscale wires to be controlled; and
one or more of field-effect junctions connected with the fourth plurality of nanoscale wires, allowing the fourth plurality of nanoscale wires to be controlled.
26. The PLA of claim 23, wherein:
one or more nanoscale wires of the second plurality of nanoscale wires comprise first controllable regions, wherein the first controllable regions, in conjunction with a plurality of voltages, invert the signals on the PLA inputs along the nanoscale wires of the second plurality of nanoscale wires; and
one or more nanoscale wires of the third plurality of nanoscale wires comprise second controllable regions, wherein the second controllable regions, in conjunction with a plurality of voltages, non-invert the signals on the PLA inputs along the nanoscale wires of the third plurality of nanoscale wires.
27. The PLA of claim 26, further comprising:
a restoring inverting arrangement connected with the PLA inputs, comprising a fifth plurality of nanoscale wires, the restoring inverting arrangement restoring the signals on the PLA inputs and inverting the signals on the PLA inputs; and
a restoring non-inverting arrangement connected with the PLA inputs, comprising a sixth plurality of nanoscale wires, the restoring non-inverting arrangement restoring signals on the PLA inputs without inverting the signals on the PLA inputs.
28. The PLA of claim 27, further comprising:
a third plurality of programmable ON-OFF devices associated with crossings between the first and fifth plurality of nanoscale wires;
a fourth plurality of programmable ON-OFF devices associated with crossings between the first and sixth plurality of nanoscale wires;
one or more field-effect junctions connected with the fifth plurality of nanoscale wires, allowing the fifth plurality of nanoscale wires to be controlled; and
one or more field-effect junctions connected with the sixth plurality of nanoscale wires, allowing the sixth plurality of nanoscale wires to be controlled.
29. The PLA of claim 28, wherein
one or more nanoscale wires of the fifth plurality of nanoscale wires comprise controllable regions, wherein the controllable regions, in conjunction with a plurality of voltages, invert the signals along the nanoscale wires of the fifth plurality of nanoscale wires; and
one or more nanoscale wires of the sixth plurality of nanoscale wires comprise controllable regions, wherein the controllable regions, in conjunction with a plurality of voltages, non-invert the signals along the nanoscale wires of the sixth plurality of nanoscale wires.
30. An electric circuit comprising programmable logic arrays (PLAs) wherein:
each PLA comprises nanoscale wires forming PLA inputs and at least one between a restoring inverting stage and a restoring non-inverting stage, the restoring inverting stage and the restoring non-inverting stage comprising nanoscale wires and restoring or inverting signals, respectively, of the PLA inputs;
each PLA comprises programmable ON-OFF devices associated with crosspoints between the nanoscale wires, forming ON-OFF stages; and
an output of at least one PLA is an input to at least one other PLA.
31. The electric circuit of claim 30, further comprising one or more isolation transistors associated with the PLA inputs and PLA outputs.
32. The electric circuit of claim 31, wherein the isolation transistors route connections between the PLA inputs, the PLA outputs, and the PLAs.
33. The electric circuit of claim 32, where the PLA outputs are computed from the PLA inputs, and which, in turn, become PLA inputs.
34. The electric circuit of claim 33, where signal conduction through a series of PLAs returns to the input of an earlier PLA, thus forming signal cycles.
35. The electric circuit of claim 34, wherein the signal cycles have variable length.
36. The electric circuit of claim 35, wherein signal conduction along the signal cycles goes through a plurality of ON-OFF and restoring stage pairs.
37. The electric circuit of claim 32, wherein signal conduction along signal cycles goes through a plurality of ON-OFF and restoring stage pairs.
38. The electric circuit of claim 30, further comprising microscale wires controlling the ON-OFF stages.
39. The electric circuit of claim 30, wherein the nanoscale wires are stochastically assembled to provide nanoscale wire addressability.
40. The electronic circuit of claim 30, wherein nanoscale wires of two different PLAs are shared between the two different PLAs.
41. The electronic circuit of claim 40, wherein sharing of nanoscale wires between the two different PLAs is obtained through isolation transistors.
42. The electronic circuit of claim 41, wherein the sharing of nanoscale wires allows two or more PLAs to be programmed from a same set of microscale wires.
43. A method of building a programmable logic array (PLA), the method comprising:
providing a first plurality of nanoscale wires forming PLA inputs;
providing a restoring inverting arrangement connected with the PLA inputs, the restoring inverting arrangement comprising a second plurality of nanoscale wires and restoring signals on the PLA inputs and inverting the signals on the PLA inputs.
44. The method of claim 43, further comprising:
providing a restoring non-inverting arrangement connected with the PLA inputs, the restoring non-inverting arrangement comprising a third plurality of nanoscale wires and restoring the signals on the PLA inputs without inverting the signals on the PLA inputs.
45. The method of claim 43, further comprising:
providing a fourth plurality of nanoscale wires crossing the second plurality of nanoscale wires.
46. The method of claim 44, further comprising:
providing a fourth plurality of nanoscale wires crossing the second plurality of nanoscale wires and the third plurality of nanoscale wires.
47. The method of claim 45 further comprising:
providing programmable ON-OFF devices associated with crossings between the second and fourth plurality of nanoscale wires.
48. The method of claim 47, further comprising:
providing microscale addressing of the first and fourth plurality of nanoscale wires allowing the programmable ON-OFF devices to be set to their ON or OFF state.
49. The method of claim 48, further comprising:
providing the nanoscale wires with axially doped regions; and
stochastically assembling the nanoscale wires.
50. The method of claim 49 where the stochastically assembled, axially doped nanoscale wires provide microscale addressing.
51. The method of claim 46 further comprising:
providing programmable ON-OFF devices associated with crossings between the second and fourth plurality of nanoscale wires and crossings between the third and fourth plurality of nanoscale wires.
52. The method of claim 47, wherein the ON-OFF devices are diodes.
53. The method of claim 51, wherein the ON-OFF devices are diodes.
54. The method of claim 1, further comprising:
providing controllable regions on one or more nanoscale wires of the second plurality of nanoscale wires.
55. The method of claim 54, further comprising:
stochastically assembling the nanoscale wires of the second plurality of nanoscale wires, wherein stochastic selection of nanoscale wires of the second plurality of nanoscale wires by means of the controllable regions is used to build the restoring arrangement.
56. The method of claim 2 further comprising:
providing controllable regions on one or more nanoscale wires of the second and third plurality of nanoscale wires.
57. The method of claim 56, further comprising:
stochastically assembling the nanoscale wires of the second and third plurality of nanoscale wires, wherein stochastic selection of nanoscale wires of the second plurality of nanoscale wires by means of the controllable regions is used to build the restoring arrangement.
58. The method of claim 54 further comprising:
applying voltages for the controllable regions so that the controllable regions invert the signals on the PLA inputs along the nanoscale wires of the second plurality of nanoscale wires.
59. The method of claim 56 further comprising:
applying voltages for the controllable regions so that the controllable regions invert or non-invert the signals on the PLA inputs along the nanoscale wires of the second and third plurality of nanoscale wires, respectively.
60. The method of claim 54, wherein the controllable regions are distributed along a portion of the nanoscale wires of the second plurality of nanoscale wires.
61. The method of claim 60, wherein the nanoscale wires of the second plurality of nanoscale wires are stochastically assembled.
62. The method of claim 56, wherein the controllable regions are distributed along a portion of the nanoscale wires of the second and third plurality of nanoscale wires.
63. The method of claim 62, wherein the nanoscale wires of the second and third plurality of nanoscale wires are stochastically assembled.
64. The method of claim 1, further comprising:
connecting a plurality of ohmic contacts with the PLA inputs, allowing the PLA inputs to be selected.
65. The method of claim 2, further comprising:
connecting a plurality of ohmic contacts with the PLA inputs, allowing the PLA inputs to be selected.
66. The method of claim 64 wherein the ohmic contacts are nanoscale ohmic contacts.
67. The method of claim 64 wherein the ohmic contacts are lithographic ohmic contacts.
68. The method of claim 64, further comprising:
selecting the PLA inputs through the ohmic contacts by the means of controllable regions located along portions of nanoscale wires of the first plurality of nanoscale wires.
69. A method of placing a signal on a nanoscale wire forming an input of a programmable logic array (PLA), the method comprising:
providing a plurality of nanoscale wires forming PLA inputs, wherein each of the nanoscale wires forming PLA inputs comprises one or more controllable regions;
crossing a plurality of ohmic contacts with the controllable regions of the nanoscale wires forming PLA inputs;
applying a first voltage to the nanoscale wires forming PLA inputs;
providing ohmic contacts to correspond with the controllable regions of at least one nanoscale wire forming a PLA input;
applying a second voltage to some of the ohmic contacts; and
applying a third voltage to the remaining ohmic contacts.
70. A method of inverting and restoring an input signal, the method comprising:
providing a first plurality of nanoscale wires forming PLA inputs;
providing a second plurality of nanoscale wires, wherein each nanoscale wire of the second plurality of nanoscale wires comprises a first end point, a second end point, at least two field effect junctions between the first end point and the second end point, and one or more controllable regions between the at least two field effect junctions;
providing ohmic contacts at the first and second endpoints;
crossing the controllable regions of the second plurality of nanoscale wires with the first plurality of nanoscale wires;
applying a first and second voltages to the at least two field effect junctions so as to discharge any residual voltage on the second plurality of nanoscale wires;
applying a signal to the first plurality of nanoscale wires forming PLA inputs; and
applying a third voltage and a fourth voltage to the first end point and the second end point, respectively, so as to cause the signal to be inverted on one of the nanoscale wires in the second plurality of nanoscale wires.
71. The method of claim 70, wherein a voltage range to gate conduction is different from a voltage range used by the nanoscale wires, to allow the at least two field effect junctions to be self aligned.
72. A method of non-inverting and restoring an input signal, the method comprising:
providing a first plurality of nanoscale wires forming inputs of a programmable logic array (PLA);
providing a second plurality of nanoscale wires, wherein each nanoscale wire of the second plurality of nanoscale wires comprises a first end point, a second end point, at least two field effect junctions between the first end point and the second end point, and one or more controllable regions between the at least two field effect junctions;
crossing the controllable regions of the second plurality of nanoscale wires with the first plurality of nanoscale wires;
applying a first and second voltages to the at least two field effect junctions so as to discharge any residual voltage on the second plurality of nanoscale wires;
applying a signal to the first plurality of nanoscale wires forming PLA inputs; and
applying a third voltage and a forth voltage to the first end point and the second end point, respectively, so as to cause the signal to be non-inverted on one of the nanoscale wires in the second plurality of nanoscale wires.
73. The method of claim 72, wherein a voltage range to gate conduction is different from a voltage range used by the nanoscale wires, to allow the at least two field effect junctions to be self aligned.
74. A method of OR-ing input signals, the method comprising:
providing a first plurality of nanoscale wires forming inputs of an OR function;
providing a second plurality of nanoscale wires forming outputs of the OR function, wherein each nanoscale wire of the second plurality of nanoscale wires comprises a first end point, a second end point, and at least one field effect junction between the first end point and the second end point;
crossing the first plurality of nanoscale wires with the second plurality of nanoscale wires so that a plurality of crossing points are disposed between the at least one field effect junction and the first end point;
providing ON-OFF devices;
electrically connecting the first plurality of nanoscale wires with the second plurality of nanoscale wires at the plurality of crossing points through the ON-OFF devices;
applying a first voltage to the at least one field effect junction, so as to discharge any residual voltage on the second plurality of nanoscale wires;
applying a second voltage to the second end; and
applying one or more signals to the first plurality of nanoscale wires forming inputs of the OR function so as to cause the one or more signals to be OR-ed on one of the nanoscale wires in the second plurality of nanoscale wires.
75. The method of claim 74, wherein a voltage range to gate conduction is different from a voltage range used by the nanoscale wires, to allow the at least two field effect junctions to be self aligned.
76. A method of AND-ing input signals, the method comprising:
providing a first plurality of nanoscale wires forming inputs of an AND function;
providing a second plurality of nanoscale wires forming outputs of the AND function, wherein each nanoscale wire of the second plurality of nanoscale wires comprises a first end point, a second end point, and at least one field effect junction between the first end point and the second end point;
crossing the first plurality of nanoscale wires with the second plurality of nanoscale wires so that a plurality of crossing points are disposed between the at least one field effect junction and the first end point;
providing ON-OFF devices;
electrically connecting the first plurality of nanoscale wires with the second plurality of nanoscale wires at the plurality of crossing points through the ON-OFF devices;
applying a first voltage to the at least one field effect junction, so as to charge the second plurality of nanoscale wires;
applying a second voltage to the second end; and
applying one or more signals to the first plurality of nanoscale wires forming inputs of the AND function so as to cause the one or more signals to be AND-ed on one of the nanoscale wires in the second plurality of nanoscale wires.
77. A method for testing for a valid address, the method comprising:
providing a first plurality of nanoscale wires forming inputs of a programmable logic array (PLA), wherein each of the nanoscale wires forming PLA inputs comprises a first end, a second end, and one or more controllable regions disposed between the first end and the second end;
crossing a plurality of ohmic contacts with the controllable regions of the first plurality nanoscale wires forming PLA inputs;
grounding the second end of the first plurality nanoscale wires forming PLA inputs;
disconnecting the second end of the first plurality nanoscale wires forming PLA inputs from a voltage supply;
applying one or more first voltages to the controllable regions for an address to be tested;
applying a second voltage to the first end of the first plurality nanoscale wires forming PLA inputs; and
measuring the second end of the first plurality nanoscale wires forming PLA inputs to test presence of the second voltage.
78. A method for testing restoration of an input signal from a valid address, the method comprising:
providing a first plurality of nanoscale wires forming inputs of a programmable logic array (PLA) comprising a first end, a second end, a field effect junction between the first end and the second end, and a programming region at the first end;
providing a second plurality of restoring nanoscale wires comprising a top end, a bottom end, one or more control regions between the top end and the bottom end;
crossing the control regions of the second plurality of restoring nanoscale wires with the first plurality of nanoscale wires forming PLA inputs;
setting the top end to a low voltage;
driving the bottom end to the low voltage;
releasing the bottom end from the low voltage;
setting all the nanoscale wires high by applying a high voltage to the first end, the second end and the field effect junction;
release the first end, the second end and the field effect junction from the high voltage;
applying a valid address to the programming region;
applying the low voltage to the programming region;
applying the high voltage to the top end; and
measuring the bottom end of the second plurality nanoscale wires for the high voltage.
79. A method for implementing a circuital logic at nanoscale level, comprising:
providing microscale wires;
providing nanoscale wires associated with the microscale wires;
forming nano-nanoscale crosspoints between nanoscale wires and nanoscale wires; and
programming the nano-nanoscale crosspoints.
80. The method of claim 79, wherein the nano-nanoscale crosspoints are formed by means of controllable regions axially distributed on the nanoscale wires.
81. The method of claim 79, further comprising:
identifying functioning nanoscale wires among the nanoscale wires.
82. A method for restoring nanoscale signals, comprising:
providing nanoscale input wires adapted to carry input signals to be restored;
providing nanoscale output wires to provide restored outputs;
crossing the nanoscale input wires with the nanoscale output wires, thus forming crossing regions;
providing ohmic contacts to power supplies, associated with the nanoscale output wires; and
providing field-effect control lines, associated with the nanoscale output wires.
83. The method of claim 82, wherein the nanoscale input wires are orthogonally crossed with the nanoscale output wires.
84. The method of claim 82, wherein the nanoscale output wires comprise controllable regions.
85. The method of claim 84, wherein the controllable regions are manufactured into the nanoscale wires during construction.
86. The method of claim 85, wherein the nanoscale output wires are assembled by random selection from a collection of nanoscale wires with controllable regions.
87. The method of claim 84, wherein the controllable regions are in proximity of the crossing regions.
88. The method of claim 84, wherein placement of the controllable regions is varied by random alignment of the nanoscale output wires.
89. A programming region for a sublithographic programmable logic array (PLA), wherein the PLA comprises a first set of nanoscale wires and a second set of nanoscale wires intersecting the first set of nanoscale wires, the programming region comprising:
a set of microscale wires crossing the first set of nanoscale wires; and
controllable regions distributed along the nanoscale wires of the first set of nanoscale wires, allowing the nanoscale wires to be controlled by means of signals input to the set of microscale wires,
wherein the signals input to the set of microscale wires allow at least one of the nanoscale wires of the first set of nanoscale wires to be programmed with a signal used as an input for the PLA.
90. A plurality of programmable logic arrays (PLAs), each PLA comprising a first set of nanoscale wires, a second set of nanoscale wires intersecting the first set of nanoscale wires, and a programming region, wherein:
first sets of nanoscale wires for different PLAs being shared among the different PLAs, thus forming a common set of nanoscale wires; and
the programming region is shared among the PLAs.
91. The plurality of PLAs of claim 90, wherein the programming region is shared among the PLAs through the common set of nanoscale wires.
92. The plurality of PLAs of claim 91, wherein the programming region comprises:
a set of microscale wires crossing the common set of nanoscale wires; and
controllable regions distributed along the nanoscale wires of the common set of nanoscale wires, allowing the nanoscale wires to be controlled by means of signals input to the set of microscale wires,
wherein the signals input to the common set of microscale wires allow at least one of the nanoscale wires of the common set of nanoscale wires to be programmed with a signal used as an input for the PLA.
93. The plurality of PLAs of claim 92, further comprising isolation transistors to allow independent functioning of individual PLAs of the plurality of PLAs.
94. The plurality of PLAs of claim 93, wherein the isolation transistors are disposed along the common set of nanoscale wires between the individual PLAs.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method of conducting a cardholder transaction, the method comprising:
presenting information stored on a card, in electronic form for review by an adjudicator;
sensing identification of the adjudicator reviewing the information at the time the information is presented; and
authorizing the completion of a transaction in response to receipt of said identification of said adjudicator.
2. A method of conducting a cardholder transaction, the method comprising:
authorizing a transaction to proceed in response to receiving an identification of an adjudicator confirming that computer readable information retrieved from a card matches a feature of a bearer of the card while said information is being presented to said adjudicator.
3. The method of claim 2 further comprising receiving data stored on said card to enable a representation of said data to be presented to said adjudicator to permit said adjudicator to compare said representation with said feature of said bearer of the card.
4. The method of claim 2 further comprising receiving said identification of said adjudicator.
5. The method of claim 4 wherein receiving said identification comprises receiving said identification while said information is being presented to said adjudicator.
6. The method of claim 2 wherein authorizing comprises enabling a message relating to said transaction to be transmitted to an account service.
7. The method of claim 2 further comprising preventing the transaction from proceeding unless an identity of said adjudicator is received.
8. The method of claim 2 wherein authorizing comprises associating the transaction with said adjudicator.
9. The method of claim 8 wherein associating comprises associating said identification of said adjudicator with said transaction.
10. The method of claim 2 further comprising causing said information to be presented to said adjudicator.
11. The method of claim 10 wherein causing comprises producing a signal for use by an annunciation device to cause said annunciation device to present said information to said adjudicator.
12. The method of claim 11 wherein causing comprises producing said annunciation signal in response to information received from said card.
13. The method of claim 2 further comprising receiving a personal identification number from said bearer of the card and preventing said personal identification number from being passed to a point of transaction terminal unless said identification of said adjudicator is received.
14. The method of claim 2 further comprising preventing transaction data from being transmitted to a transaction processor unless an adjudicator is identified while said information is being presented.
15. The method of claim 2 further comprising acquiring transaction data representing the transaction and associating said identification of said adjudicator with said transaction data.
16. The method of claim 15 further comprising producing a transaction record associating said identification of said adjudicator with said transaction data.
17. The method of claim 16 further comprising causing said transaction record to be stored.
18. The method of claim 2 further comprising reading data stored on said card to enable a representation of said data to be presented to said adjudicator to permit said adjudicator to compare said representation with said feature of said bearer of the card.
19. The method of claim 18 wherein reading comprises retrieving an image file representing an image from said card.
20. The method of claim 19 further comprising causing said image to be presented to said adjudicator.
21. The method of claim 20 further comprising producing a representation of said image for viewing by said adjudicator.
22. The method of claim 21 further comprising sensing an identity of said adjudicator while said image is being presented to produce said identification of said adjudicator.
23. The method of claim 18 wherein reading comprises retrieving an audio file from said card.
24. The method of claim 18 wherein reading comprises retrieving a fingerprint file from said card.
25. The method of claim 2 wherein receiving said confirmation comprises sensing an identity of said adjudicator.
26. The method of claim 25 wherein sensing comprises receiving an identification code associated with said adjudicator.
27. The method of claim 25 wherein sensing comprises reading, from a computer readable medium, an identification code identifying said adjudicator.
28. The method of claim 25 wherein sensing comprises producing a representation of a fingerprint of said adjudicator and comparing said representation to a reference fingerprint to determine the identity of said adjudicator.
29. The method of claim 25 wherein sensing comprises producing a representation of a signature of said adjudicator and comparing said signature to a reference signature representation to determine the identity of said adjudicator.
30. The method of claim 25 wherein sensing comprises producing a representation of an audio signature of said adjudicator and comparing said signature to a reference audio signature representation to determine the identity of said adjudicator.
31. The method of claim 25 wherein sensing comprises producing a representation of an iris signature of said adjudicator and comparing said representation with a reference iris signature representation to determine the identity of said adjudicator.
32. The method of claim 25 wherein sensing comprises receiving a key code from a key sensor operable to sense a key associated with said adjudicator.
33. An apparatus for controlling a cardholder transaction, the apparatus comprising:
a card interface for receiving an indication that information stored on a card is being presented to an adjudicator;
an identification interface for receiving an identification of said adjudicator confirming that said information stored on said card matches a feature of a bearer of the card; and
a transaction controller operable to produce a signal indicative of whether or not a transaction should proceed, in response to whether or not said identification of said adjudicator is received while said information is being presented to said adjudicator.
34. The apparatus of claim 33 wherein said transaction controller is operable to prevent the transaction from proceeding unless said identification is received while said information is being presented to said adjudicator.
35. The apparatus of claim 34 wherein said transaction controller produces an authorization signal representing whether or not the transaction is to proceed.
36. The apparatus of claim 33 wherein said transaction controller further comprises a transaction interface for receiving a transaction signal and wherein said transaction controller is operable to selectively permit said transaction signal to be communicated to a transaction processor, in response to said authorization signal.
37. The apparatus of claim 33 further comprising an annunciation controller for controlling annunciation of information retrieved from said card.
38. The apparatus of claim 33 further comprising an annunciator interface for receiving information stored on said card and for producing an annunciation signal in response to said information stored on said card.
39. The apparatus of claim 38 wherein said annunciation signal is operable to control an annunicator to annunciate said information.
40. The apparatus of claim 39 wherein said annunication signal is operable to cause an image derived from said information to be produced on a display.
41. The apparatus of claim 33 further comprising a transaction interface for receiving a transaction message and wherein said transaction controller is operable to control whether or not said transaction message is transmitted to a transaction processor.
42. The apparatus of claim 41 wherein said transaction controller is operable to associate said identification of said adjudicator with said transaction message.
43. The apparatus of claim 42 further comprising a storage device for storing a transaction record associating said identification of said adjudicator with said transaction message.
44. The apparatus of claim 33 further comprising an identification code interface operable to receive a code from said bearer of the card and wherein said transaction controller is operable to prevent said code from being passed to a point of transaction terminal unless said identification of said adjudicator is received.
45. The apparatus of claim 33 further comprising a card reader in communication with said card interface, for reading data stored on said card to enable a representation of said data to be presented to said adjudicator to permit said adjudicator to compare said representation with said feature of said bearer of the card.
46. The apparatus of claim 45 further comprising a card reader driver operable to control said card reader to retrieve an image file from said card.
47. The apparatus of claim 46 further comprising an annunication interface operable to receive said image file from said card reader interface and to provide said image file to an annunciator to cause said image to be presented to said adjudicator.
48. The apparatus of claim 47 further comprising an annunciator in communication with said annunciator interface for producing a representation of said image file for viewing by said adjudicator.
49. The apparatus of claim 47 wherein said transaction controller is operable to receive said identification of said adjudicator while said image is being presented.
50. The apparatus of claim 45 wherein said card reader driver is operable to control said card reader to retrieve an audio file from said card.
51. The apparatus of claim 45 wherein said card reader driver is operable to control said card reader to retrieve a fingerprint file from said card.
52. The apparatus of claim 33 further comprising a sensor in communication with said identification interface for sensing an identity of said adjudicator.
53. The apparatus of claim 52 wherein said sensor is operable to receive an identification code associated with said adjudicator.
54. The apparatus of claim 52 wherein said sensor is operable to read said identification code from a computer readable medium.
55. The apparatus of claim 52 wherein said sensor is operable to produce a representation of a fingerprint of said adjudicator and wherein said identification interface is operable to compare said fingerprint representation with a reference fingerprint representation to determine the identity of said adjudicator.
56. The apparatus of claim 52 wherein said sensor is operable to produce a representation of a signature of said adjudicator and wherein said identification interface is operable to compare said signature representation with a reference signature representation to determine the identity of said adjudicator.
57. The apparatus of claim 52 wherein said sensor is operable to producing a representation of an audio signature of said adjudicator and wherein said identification interface is operable to compare said audio signature representation with a reference audio signature representation to determine the identity of said adjudicator.
58. The apparatus of claim 52 wherein said sensor is operable to produce a representation of an iris signature of said adjudicator and wherein said identification interface is, operable to compare said iris signature representation with a reference iris signature representation to determine the identity of said adjudicator.
59. The apparatus of claim 52 wherein said sensor is operable to produce a key code in response to sensing a key associated with said adjudicator.
60. A transaction system comprising the apparatus of claim 33 and further comprising a point of transaction terminal responsive to said authorization signal to selectively permit a transaction to proceed.
61. A computer readable medium operable to provide instructions to a processor circuit to direct the processor circuit to authorize a transaction to proceed in response to receiving an identification of an adjudicator confirming that computer readable information retrieved from a card matches a feature of a bearer of the card while said information is being presented to said adjudicator.
62. A signal comprising a segment representing a plurality of computer readable instructions for directing a processor circuit to authorize a transaction to proceed in response to receiving an identification of an adjudicator confirming that computer readable information retrieved from a card matches a feature of a bearer of the card while said information is being presented to said adjudicator.
63. An apparatus for controlling a cardholder transaction, the apparatus comprising:
means for receiving an indication that information stored on said card is being presented to said adjudicator;
means for receiving an identification of an adjudicator confirming that said information stored on said card matches a feature of a bearer of the card; and
means for producing a signal indicative of whether or not a transaction should proceed, in response to whether or not said identification of said adjudicator is received while said information is being presented to said adjudicator.
64. The apparatus of claim 63 wherein said means for producing is operable to prevent the transaction from proceeding unless said identification is received while said information is being presented to said adjudicator.
65. The apparatus of claim 64 wherein said means for producing is operable to produce an authorization signal representing whether or not the transaction is to proceed.
66. The apparatus of claim 63 wherein said means for producing is operable to receive a transaction signal and to selectively permit said transaction signal to be communicated to a transaction processor, in response to said authorization signal.
67. The apparatus of claim 63 further comprising means for reading said card to retrieve a feature file from said card.
68. The apparatus of claim 67 further comprising means for annunciating information contained in said feature file.
69. The apparatus of claim 63 further comprising means for receiving a transaction message, said means being operable to control whether or not said transaction message is transmitted to a transaction processor.
70. The apparatus of claim 69 wherein said means for receiving is operable to associate an identity of said adjudicator with said transaction message.
71. The apparatus of claim 70 further comprising means for storing said transaction record.
72. The apparatus of claim 63 further comprising sensing means for sensing an identity of said adjudicator.
73. The apparatus of claim 72 wherein said sensing means is operable to produce a code identifying said adjudicator.
74. A card transaction apparatus comprising:
an input device for receiving input from a bearer of the card;
a card reader for reading a feature file from said card, said feature file including a representation of a feature of an authorized user of the card;
an annunciator for annunciating said representation of said feature in said feature file, to an adjudicator capable of confirming that the annunciated representation of said feature matches a feature of the bearer of the card;
an identification interface for receiving an identification code from said adjudicator while said representation of said feature is being annunciated; and
a transaction controller operable to cause said input from said bearer of the card received at said input device to be transmitted to a receiver, in response to receipt of an identification code at said identification interface while said representation of said feature is being annunciated.