1. A control for selectively orienting a medical device of the type having control cables secured at or adjacent a distal tip of the medical device to direct the distal tip in one or more of the updown, leftright directions, comprising:
a body;
an actuator in the body that is capable of moving independently in at least two directions;
a first pair of control cables that move when the actuator is moved in a first direction; and
a second pair of control cables that move when the actuator is moved in a second direction;
wherein at least one of the first or second pair of control cables has an inner cable and an outer sheath arranged such that one end of the inner cable and outer sheath move with respect to one another when the actuator is moved in one of said two directions and do not move with respect to each other when the actuator is moved in the other of said at least two directions.
2. The control of claim 1, further comprising:
a rail mounted to a fixed surface with respect to a patient along which the control can be moved to advance or retract the medical device.
3. The control of claim 2, further comprising means for rotating the body about a longitudinal axis of the rail.
4. The control of claim 1, further comprising means for rotating the body about a longitudinal axis of the body.
5. The control of claim 1, further comprising a trigger on the control for actuating an instrument within the medical device for performing a procedure on a patient.
6. The control of claim 1, wherein the trigger is located on the actuator.
7. The control of claim 1, wherein the trigger is located on the body.
8. A method of performing a minimally invasive procedure on a patient with two or more medical devices by:
delivering the two or more medical devices to an internal location within the patient; and
selectively controlling the medical devices with a control that comprises:
a body;
an actuator in the body that is capable of moving independently in at least two directions;
a first pair of control cables that move when the actuator is moved in a first direction; and
a second pair of control cables that move when the actuator is moved in a second direction;
wherein at least one of the first or second pair of control cables has an inner cable and an outer sheath arranged such that one end of the inner cable and outer sheath move with respect to one another when the actuator is moved in one of said two directions and do not move with respect to each other when the actuator is moved in the other of said at least two directions.
9. A control for selectively orienting a medical device, comprising:
a rail;
a control movably secured to the rail, the control including:
a body; and
an actuator within the body that is pivotally coupled to the body such that the actuator can be tilted in the body and rotationally coupled to the body so that the actuator can be rotated with respect to the body, wherein the actuator is coupled to at least two pairs of control cables in the medical device that control the orientation of the medical device such that tilting of the actuator causes the medical device to move in one plane and rotation of the actuator causes the medical device to move in another plane.
10. The control of claim 9, wherein the actuator is coupled to the body with a ball joint.
11. The control of claim 9, wherein the actuator is coupled to the body with a trunnion.
12. The control of claim 10, wherein the actuator is coupled to a cable stop that moves with the actuator and the control cables include two or more bowden cables coupled to the cable stop.
13. The control of claim 10, wherein the actuator is coupled to a cable stop that moves with the actuator and the control cables include two or more bowden cables that move the medical device in one of said planes that are coupled to the cable stop.
14. The control of claim 9, further comprising a trigger on the control for actuating an instrument within the medical device for performing a procedure on a patient.
15. The control of claim 14, wherein the trigger is on the body.
16. The control of claim 14, wherein the trigger is on the actuator.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An interface circuit configured to manage refresh command sequences, the interface circuit comprising:
a system interface adapted to receive a refresh command from a memory controller;
a means for determining the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller; and
at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.
2. The interface circuit of claim 1, further comprising:
a measurement unit configured to perform analog signal measurements and to determine a configuration of the two or more memory devices; and
a calculation unit configured to determine the timing for issuing staggered refresh commands to the two or more memory devices based on measurements received from the measurement unit and the refresh command received from the memory controller.
3. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine analog pin characteristics of the two or more memory devices.
4. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine timing responses at selected logic threshold levels.
5. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of analog measurements to determine a timing response at a peak detected voltage change, a duration and a response ring.
6. The interface circuit of claim 2, wherein the measurement unit is further configured to perform a series of measurements to determine an operating of each of the two or more memory devices.
7. The interface circuit of claim 1, further comprising a means for computing two staggered refresh cycles for the two memory devices that are staggered by an amount of time equal to approximately half a single refresh cycle associated with the refresh command received from the memory controller.
8. The interface circuit of claim 1, further comprising a means for computing four staggered refresh cycles for eight memory devices coupled to the interface circuit that are staggered by an amount of time equal to approximately a quarter of a single refresh cycle associated with the refresh command received from the memory controller.
9. The interface circuit of claim 1, further comprising a means for computing eight staggered refresh cycles for sixteen memory devices coupled to the interface circuit that are staggered by an amount of time equal to approximately an eighth of a single refresh cycle associated with the refresh command received from the memory controller.
10. The interface circuit of claim 1, further comprising a means for determining optimized timing for staggered refresh operations that minimize instantaneous power supply load.
11. The interface circuit of claim 1, wherein the system interface further comprises a memory address signal interface, a memory control signal interface, a memory clock signal interface, and a memory data signal interface.
12. The interface circuit of claim 1, further comprising emulation logic capable of emulating an interface protocol of each of the two or more memory devices.
13. The interface circuit of claim 1, further comprising a scheduler configured to order the staggered refresh commands being generated for the two or more memory devices.
14. The interface circuit of claim 1, wherein the two or more memory devices are arranged in one or more stacks, and each staggered refresh cycle is transmitted to two memory devices residing within the same stack.
15. The interface circuit of claim 14, wherein each of the two or more memory devices comprises a dynamic random access memory chip.
16. The interface circuit of claim 14, wherein the two or more memory devices are arranged in one stack, and the interface circuit is integrated within the one stack.
17. The interface circuit of claim 16, wherein the interface circuit comprises an intelligent buffer chip.
18. The interface circuit of claim 17, wherein the two or more memory devices comprise dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line memory module.
19. The interface circuit of claim 1, wherein the interface circuit is coupled directly to a memory module.
20. The interface circuit of claim 19, wherein the memory module comprises a dual in-line memory module.
21. The interface circuit of claim 1, wherein the interface circuit is connected to a circuit board.
22. The interface circuit of claim 1, wherein the interface circuit is included within a computing device.