1. A conversion circuit comprising:
(a) a coarse-resolution quantization circuit including
i. a resistor string including a plurality of resistors and a plurality of tap points between the various resistors, and
ii. a plurality of coarse-resolution comparators, each coarse-resolution comparator having a first input coupled to receive an input voltage and a second input coupled to a corresponding coarse-resolution tap point, each coarse-resolution comparator being operable during a first phase to produce a first logic level only if the input voltage exceeds a voltage of the coarse-resolution tap point coupled to the second input of that coarse-resolution comparator; and
(b) a fine-resolution quantization circuit including
i. a plurality of fine-resolution comparators each having a first input coupled to receive the input voltage, each fine-resolution comparator being operable during a second phase to produce a fine-resolution output logic level indicative of whether the input voltage exceeds a voltage of a tap point coupled to a second input of that fine-resolution comparator, and
ii. a control circuit operative to selectively couple the second input of each fine-resolution comparator to a corresponding tap point of a group of tap points located immediately below a coarse-resolution tap point coupled to a highest coarse-resolution comparator producing the first logic level, the output logic levels of the fine-resolution comparators and the coarse-resolution comparators up to and including the highest coarse-resolution comparator producing the first logic level representing a thermometer code representation of a quantized value of the input voltage.
2. The conversion circuit of claim 1 wherein a group of tap points is located immediately below each coarse-resolution tap point, respectively, wherein the control circuit includes a plurality of groups of switches, each group of switches corresponding to a group of the tap points, respectively, wherein in each group of switches a first terminal of each switch is coupled to a corresponding tap point and a second terminal of that switch is coupled to the second input of a corresponding fine-resolution comparator, respectively.
3. The conversion circuit of claim 2 wherein the control circuit includes a plurality of exclusive OR circuits, each exclusive OR circuit having a pair of inputs coupled to outputs of a pair of adjacent coarse-resolution comparators, respectively, to determine if output logic levels thereof are equal, an output of each exclusive OR circuit being coupled to control electrodes of the switches of a corresponding group, respectively, to close the switches in that group when the output logic levels of the adjacent coarse-resolution comparators are different.
4. The conversion circuit of claim 3 further including a plurality of interpolation circuits each having a first pair of inputs coupled to outputs of a pair of adjacent coarse-resolution comparators, respectively, each interpolation circuit being coupled to the output of a corresponding exclusive OR circuit, respectively, to produce a plurality of interpolation quantization levels between quantization levels represented by the outputs of a corresponding pair of adjacent coarse-resolution comparators.
5. The conversion circuit of claim 3 wherein each exclusive OR circuit includes an exclusive NOR gate.
6. The conversion circuit of claim 4 wherein each fine-resolution comparator has a disable input for reducing power consumption therein.
7. The conversion circuit of claim 4 wherein each interpolation circuit includes
(1) an AND function circuit for performing a logical ANDing of the output levels of a corresponding pair of adjacent coarse-resolution comparators; and
(2) a plurality of switch circuits each including
i. a first switch coupled between an output of the AND function circuit and a corresponding quantization level conductor,
ii. a second switch coupled between an output of a corresponding fine-resolution comparator and the corresponding quantization level conductor, and
iii. the first switch being operable to couple a logic level equal to the first logic level to the corresponding quantization level conductor when output levels of the corresponding pair of adjacent coarse-resolution quantization circuits are equal, the second switch being operable to couple the output of the corresponding fine-resolution comparator to the corresponding quantization level conductor when the output levels of the corresponding pair of adjacent coarse-resolution quantization circuits are different.
8. The conversion circuit of claim 7 wherein all of the logic levels produced by the coarse-resolution comparators and the fine-resolution comparators together constitute the thermometer code representation of the input voltage.
9. The conversion circuit of claim 1 further, including a delta-sigma modulator, and wherein the coarse-resolution quantization circuit and the fine-resolution quantization circuit are included as a two-phase quantizer of the delta-sigma modulator.
10. The conversion circuit of claim 9 further including a decimation filter coupled to an output of the two-phase quantizer such that the conversion circuit is a delta-sigma ADC.
11. The conversion circuit of claim 1 wherein the number of tap points of each group is equal to the number of fine-resolution comparators.
12. The conversion circuit of claim 7 wherein the first logic level is a logical \u201c1\u201d level.
13. The conversion circuit of claim 1 further including 4 of the course-resolution comparators and 3 of the fine-resolution comparators.
14. The conversion circuit of claim 4 wherein on all of the course-resolution comparators provide an immediate initial DC operational point for the course-resolution quantization circuit during start-up operation.
15. The conversion circuit of claim 9 wherein the delta sigma modulator is a fifth order feed-forward delta-sigma modulator.
16. A method of quantizing an analog input signal, comprising:
(a) during a first phase time, coupling a first input of each of a plurality of coarse-resolution comparators to the input voltage, wherein a second input of each coarse-resolution comparator is coupled to a plurality of corresponding coarse tap points, respectively, of a resistor string which also includes a plurality of intermediate tap points to cause each coarse-resolution comparator to produce a first logic level only if the input voltage exceeds a voltage of the coarse-resolution tap point coupled to the first input of that course-resolution comparator; and
(b) during a second phase time which follows the first phase time,
i. coupling a first input of each of a plurality of fine-resolution comparators to the input voltage, and
ii. selectively coupling a second input of each fine-resolution comparator to a corresponding tap point of a group of tap points located immediately below a coarse-resolution tap point coupled to a highest coarse-resolution comparator producing the first logic level to cause each fine-resolution comparator to produce a second logic level indicative of whether the input voltage exceeds a voltage of the tap point coupled to the second input of that fine-resolution comparator,
wherein output logic levels of the fine-resolution comparators and the coarse-resolution comparators up to and including the highest coarse-resolution comparator producing the first logic level together represent a thermometer code representation of the input voltage.
17. A circuit for quantizing an analog input signal, comprising:
(a) means for coupling a first input of each of a plurality of coarse-resolution comparators to the input voltage during a first phase time, wherein a second input of each coarse-resolution comparator is coupled to a plurality of corresponding coarse tap points, respectively, of a resistor string which also includes a plurality of intermediate tap points to cause each coarse-resolution comparator to produce a first logic level only if the input voltage exceeds a voltage of the coarse-resolution tap point coupled to the first input of that course-resolution comparator;
(b) a plurality of fine-resolution comparators each having a first input coupled to the input voltage; and
(c) means for selectively coupling a second input of each fine-resolution comparator to a corresponding tap point of a group of tap points located immediately below a coarse-resolution tap point coupled to a highest coarse-resolution comparator producing the first logic level to cause each fine-resolution comparator to produce a second logic level indicative of whether the input voltage exceeds a voltage of the tap point coupled to the second input of that fine-resolution comparator during a second phase time which follows the first phase time,
wherein output logic levels of the fine-resolution comparators and the coarse-resolution comparators up to and including the highest coarse-resolution comparator producing the first logic level together represent a thermometer code representation of the input voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A non-volatile semiconductor memory comprising:
a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array; and
a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.
2. A non-volatile semiconductor memory according to claim 1, wherein when write of data is executed to the cell transistors of the number-of-rewrites storage regions in the non-selected memory cell arrays at the voltage lower than the ordinary write voltage, the write of data is executed making use of 1 write stress to the cell transistors by applying a predetermined power-supply voltage to bit lines connected in series to the cell transistors and applying a write voltage Vpgm to the gates of the cell transistors.
3. A non-volatile semiconductor memory according to claim 2, wherein sense amplifiersdata registers are provided to corresponding bit lines in the memory cell arrays, and the power-supply voltage to the bit lines are supplied from the sense amplifiersdata registers.
4. A non-volatile semiconductor memory according to claim 1, wherein when write of data is executed to the cell transistors of the number-of-rewrites storage regions in the non-selected memory cell arrays at the voltage lower than the ordinary write voltage, the write of data is executed making use of Vpass stress to the cell transistors by applying a non-selected memory cell voltage Vpass lower than the write voltage to the control gates of the cell transistors and applying ground potential Gnd to bit lines connected in series to the cell transistors.
5. A non-volatile semiconductor memory according to claim 4, wherein sense amplifiersdata registers are provided to corresponding bit lines in the memory cell arrays, and the ground voltage to the bit lines are supplied from the sense amplifiersdata registers.
6. A non-volatile semiconductor memory according to claim 1, wherein, when the number of data rewrites is read out from the cell transistors of the number-of-rewrites storage regions which stores the number of data rewrites, read out data is output to the outside of the device.
7. A non-volatile semiconductor memory according to claim 6, wherein the number of data rewrites is determined by determining a center of distribution of threshold values of the plurality of cell transistors based on data read out from the plurality of cell transistors.
8. A non-volatile semiconductor memory according to claim 6, wherein a counter is provided so as to be used when the number of data rewrites is read out, and, when the number of data rewrites is read out from the cell transistors of the number-of-rewrites storage regions which stores the number of data rewrites, a voltage of word lines connected to control gates of the cell transistors is changed, and a result of read of the number of data rewrites is serially output to the outside of the device as data read out for one page.
9. A non-volatile semiconductor memory according to claim 1, wherein, when the number of data rewrites is read out from the cell transistors of the number-of-rewrites storage regions which stores the number of data rewrites, a voltage of word lines connected to the control gates of the cell transistors is changed, and the number of data rewrites is determined based on the voltage of the word line at the time the number of cell transistors having a threshold value less than the voltage of the word line exceeds one half a total number of the cell transistors in the number-of-rewrites storage regions.
10. A non-volatile semiconductor memory according to claim 9, wherein the number of data rewrites is determined by determining a center of distribution of threshold values of the plurality of cell transistors based on data read out from the plurality of cell transistors.
11. A non-volatile semiconductor memory according to claim 1, wherein a counter is provided so as to be used when the number of data rewrites is read out, and, when the number of data rewrites is read out from the cell transistors of the number-of-rewrites storage regions which stores the number of data rewrites, a voltage of the word lines connected to control gates of the cell transistors is changed, and the counter is counted up when the cell transistors have a threshold value less than the voltage of the word line, and the number of data rewrites is determined based on the voltage of the word line at the time the most significant bit of the counter is inverted.
12. A non-volatile semiconductor memory according to claim 11, wherein the number of data rewrites is determined by determining a center of distribution of threshold values of the plurality of cell transistors based on data read out from the plurality of cell transistors.
13. A non-volatile semiconductor memory according to claim 1, wherein row decoders which correspond to the number-of-rewrites storage regions are provided, each of the row decoders include a fuse for use in prohibition of erase selection, and the fuse is cut off after data of the memory cells are erased when the memory is shipped.
14. A non-volatile semiconductor memory comprising:
a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding memory cell array;
a plurality of sense amplifiersdata registers commonly connected to a pair of bit lines of a pair of even and odd columns in each of the memory cell arrays; and
a number-of-rewrites write control circuit which stores, when data is written to cell transistors connected to one of the pair of bit lines of the pair of even and odd columns in the number-of-rewrites storage regions of selected memory cell arrays, the number of rewrites to the cell transistors connected to the other of the pair of bit lines by executing write by supplying the cell transistors with a voltage lower than an ordinary write voltage to so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.
15. A non-volatile semiconductor memory according to claim 14, wherein when the write of data is executed to the cell transistors connected to said other bit line at the voltage lower than the ordinary write voltage, the write of data is executed making use of 1 write stress to the cell transistors by applying a predetermined power-supply voltage to bit lines connected in series to the cell transistors and applying a write voltage Vpgm to the gates of the cell transistors.
16. A non-volatile semiconductor memory according to claim 15, wherein sense amplifiersdata registers are provided to corresponding bit lines in the memory cell arrays, and the power-supply voltage to the bit lines are supplied from the sense amplifiersdata registers.
17. A non-volatile semiconductor memory according to claim 14, wherein when the write of data is executed to the cell transistors connected to said other bit line at the voltage lower than the ordinary write voltage, the write of data is executed making use of Vpass stress to the cell transistors by applying a non-selected memory cell voltage Vpass lower than the write voltage to the control gates of the cell transistors and applying ground potential Gnd to bit lines connected in series to the cell transistors.
18. A non-volatile semiconductor memory according to claim 17, wherein sense amplifiersdata registers are provided to corresponding bit lines in the memory cell arrays, and the ground voltage to the bit lines are supplied from the sense amplifiersdata registers.
19. A non-volatile semiconductor memory according to claim 17, wherein, when the number of data rewrites is read out from the cell transistors of the number-of-rewrites storage regions which stores the number of data rewrites, read out data is output to the outside of the device.
20. A non-volatile semiconductor memory according to claim 19, wherein the number of data rewrites is determined by determining a center of distribution of threshold values of the plurality of cell transistors based on data read out from the plurality of cell transistors.
21. A non-volatile semiconductor memory according to claim 19, wherein a counter is provided so as to be used when the number of data rewrites is read out, and, when the number of data rewrites is read out from the cell transistors connected to said other bit line, a voltage of word lines connected to control gates of the cell transistors is changed, and a result of read of the number of data rewrites is serially output to the outside of the device as data read out for one page.
22. A non-volatile semiconductor memory according to claim 17, wherein, when the number of data rewrites is read out from the cell transistors of the number-of-rewrites storage regions which stores the number of data rewrites, a voltage of the word lines connected to the control gates of the cell transistors is changed, and the number of data rewrites is determined based on the voltage of the word line at the time the number of cell transistors having a threshold value less than the voltage of the word line exceeds one half the total number of the cell transistors in the number-of-rewrites storage regions.
23. A non-volatile semiconductor memory according to claim 22, wherein the number of data rewrites is determined by determining a center of distribution of threshold values of the plurality of cell transistors based on data read out from the plurality of cell transistors.
24. A non-volatile semiconductor memory according to claim 14, wherein a counter is provided so as to be used when the number of data rewrites is read out, and, when the number of data rewrites is read out from the cell transistors of the number-of-rewrites storage regions which stores the number of data rewrites, a voltage of the word lines connected to control gates of the cell transistors is changed, and the counter is counted up when the cell transistors have a threshold value less than the voltage of the word line, and the number of data rewrites is determined based on the voltage of the word line at the time the most significant bit of the counter is inverted.
25. A non-volatile semiconductor memory according to claim 24, wherein the number of data rewrites is determined by determining a center of distribution of threshold values of the plurality of cell transistors based on data read out from the plurality of cell transistors.