What is claimed is:
1. A printed circuit board to which a surface mount device having at least one terminal is to be soldered, said printed circuit board comprising:
a substrate having a mounting surface on which the surface mount device is to be mounted; and
at least one footprint arranged on the mounting surface and positioned to align with the terminal of the surface mount device, said at least one footprint comprising a plurality of patterned parts and a plurality of solder layers formed on the patterned parts, respectively, each of said patterned parts being so shaped to limit a region in which molten solder flows when the solder layer is melted.
2. A printed circuit board according claim 1, wherein the patterned parts are spaced part from one another.
3. A printed circuit board according to claim 2, wherein the patterned parts are electrically connected by bridges, and the bridges are covered with solder resist.
4. A printed circuit board according to claim 3, wherein the substrate has a conductor, and one of the patterned parts is electrically connected to the conductor.
5. A printed circuit board according to claim 1, wherein the patterned parts are circular.
6. A printed circuit board according to claim 1, wherein the patterned parts have a shape defined by a plurality of straight lines and a plurality of arcs connecting the ends of the straight lines.
7. A printed circuit board according to claim 1, wherein the patterned parts are polygonal and have at least five corners each.
8. A printed circuit board according to claim 1, wherein the terminal of the surface mount device is polygonal, and the patterned parts are arranged in rows and columns.
9. A printed circuit board according to claim 8, wherein the surface mount device generates heat while operating.
10. A printed circuit board to which a surface mount device having a plurality of leads arranged at intervals is to be soldered, said printed circuit board comprising:
a substrate having a mounting surface on which the surface mount device is to be mounted; and
a plurality of footprints arranged, side by side, on the mounting surface of the substrate and positioned to align with the leads, respectively, each of said footprints comprising a plurality of patterned parts and a plurality of solder layers formed on the patterned parts, respectively, said patterned parts being arranged in a column, spaced apart in a lengthwise direction of the lead and so shaped to limit a region in which molten solder flows when the solder layer is melted.
11. A printed circuit board according to claim 10, wherein the patterned parts are electrically connected by bridges, and the bridges are covered with solder resist.
12. A printed circuit board according to claim 10, wherein the patterned parts of each footprint stagger with respect to those of any adjacent footprint, in the lengthwise direction of the lead.
13. A circuit module comprising:
a surface mount device having at least one terminal;
a printed circuit board having a mounting surface on which the surface mount device is soldered; and
at least one footprint arranged on the mounting surface and positioned to align with the terminal of the surface mount device, said at least one footprint comprising a plurality of patterned parts and a plurality of solder layers formed on the patterned parts, respectively, each of said patterned parts being so shaped to limit a region in which molten solder flows when the solder layer is melted.
14. A circuit module according to claim 13, wherein the patterned parts are spaced part from one another.
15. A circuit module according to claim 14, wherein the patterned parts are electrically connected by bridges, one of the patterned parts is electrically connected to a conductor formed on the printed circuit board, and the bridges are covered with solder resist.
16. A method of manufacturing a printed circuit board to which a surface mount device having at least one terminal is to be soldered, said method comprising:
forming at least one footprint on a mounting surface of a substrate and in alignment with the terminal of the surface mount device, said footprint comprising a plurality of patterned parts which have a shape selected from the group consisting of a circular shape, a rectangular shape having rounded corners, and a polygonal shape having at least five corners;
coating the patterned parts with solder paste through a screen mask laid on the mounting surface of the substrate, thereby covering the patterned parts with solder layers; and
applying solder resist to the mounting surface of the substrate, except regions in which the patterned parts are provided.
17. A method of assembling a circuit module including a surface mount device having at least one terminal, said method comprising:
preparing a printed circuit board having a mounting surface on which the surface mount device is to be mounted, and at least one footprint on the mounting surface, said at least one footprint comprising a plurality of patterned parts which have a shape selected from the group consisting of a circular shape, a rectangular shape having rounded corners, and a polygonal shape having at least five corners and which are covered with solder layers;
mounting said at least one surface mount device on the mounting surface of the printed circuit board, and setting said at least one terminal in contact with the solder layers; and
heating the printed circuit board and melting the solder layers, thereby achieving reflow soldering and connecting said at least one terminal to said at least one footprint.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for expanding trenches comprising the steps of:
forming a trench in a substrate having side walls including at least two crystallographic planes, a first one of the at least two crystallographic planes being etchable at a faster rate than a second one of the at least two crystallographic planes;
selectively growing a dielectric layer on surfaces of the at least two crystallographic planes such that the dielectric layer includes a greater thickness on the first one of the at least two crystallographic planes than on the second one of the at least two crystallographic planes; and
etching the dielectric layer and the substrate such that an etch rate of the second one of the at least two crystallographic planes is effectively etched at a faster rate than the first one of the at least two crystallographic planes.
2. The method as recited in claim 1, wherein the substrate includes silicon and the first one of the at least two crystallographic planes includes a (100) plane the second one of the at least two crystallographic planes includes a (110) plane, and wherein the step of selectively growing includes selectively growing an oxide on the surfaces.
3. The method as recited in claim 1, wherein the step of etching the dielectric layer and the substrate further comprises the step of preparing surfaces within the trench by removing portions of the dielectric layer by wet etching the dielectric layer to expose portions of the substrate in the trench.
4. The method as recited in claim 3, wherein the step of etching the dielectric layer and the substrate further comprises the step of preparing the exposed portions of the substrate within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface.
5. The method as recited in claim 1, wherein the step of etching the dielectric layer and the substrate includes anisotropically wet etching the surfaces of the substrate to expand the trench.
6. The method as recited in claim 5, wherein the step of anisotropically wet etching includes the step of anisotropically wet etching by employing ammonium hydroxide.
7. The method as recited in claim 5, wherein the step of anisotropically wet etching includes the step of anisotropically wet etching in a batch process.
8. The method as recited in claim 1, wherein the step of anisotropically wet etching includes the step of expanding the trench to form rectangular-shaped trenches.
9. A method for forming expanded deep trenches for semiconductor devices comprising the steps of:
forming a trench in a substrate having side walls including at least two crystallographic planes, a first one of the at least two crystallographic planes having a first etch rate which is faster than a second etch rate for a second one of the at least two crystallographic planes;
forming a collar in an upper portion of the trench;
expanding a lower portion of the trench by:
selectively growing a dielectric layer on surfaces of the at least two crystallographic planes such that the dielectric layer includes a greater thickness on the first one of the at least two crystallographic planes than on the second one of the at least two crystallographic planes; and
etching the dielectric layer and the substrate such that an etch rate of the second one of the at least two crystallographic planes is effectively etched at a faster rate than the first one of the at least two crystallographic planes.
10. The method as recited in claim 9, wherein the substrate includes silicon and the first one of the at least two crystallographic planes includes a (100) plane the second one of the at least two crystallographic planes includes a (110) plane, and wherein the step of selectively growing includes selectively growing an oxide on the surfaces.
11. The method as recited in claim 9, wherein the step of etching the dielectric layer and the substrate further comprises the step of preparing surfaces within the trench by removing portions of the dielectric layer by wet etching the dielectric layer to expose portions of the substrate in the trench.
12. The method as recited in claim 11, wherein the step of etching the dielectric layer and the substrate further comprises the step of preparing the exposed portions of the substrate within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface.
13. The method as recited in claim 9, wherein the step of etching the dielectric layer and the substrate includes anisotropically wet etching the surfaces of the substrate to expand the trench.
14. The method as recited in claim 13, wherein the step of anisotropically wet etching includes the step of anisotropically wet etching by employing ammonium hydroxide.
15. The method as recited in claim 13, wherein the step of anisotropically wet etching includes the step of anisotropically wet etching in a batch process.
16. The method as recited in claim 9, wherein the step of anisotropically wet etching includes the step of expanding the trench to form rectangular-shaped trenches.
17. The method as recited in claim 9, further comprising the step of forming a buried plate electrode adjacent to the trench.
18. A method for forming expanded deep trenches for semiconductor devices comprising the steps of:
forming a trench in a monocrystalline silicon substrate having side walls including at least two crystallographic planes including (100) and (110) planes wherein the (100) plane is etchable at a faster rate than the (110) plane when subjected to an anisotropic wet etch;
forming an oxide collar in an upper portion of the trench;
expanding a lower portion of the trench selective to the oxide collar by:
selectively growing an oxide layer on the (100) and (110) planes such that the oxide layer includes a greater thickness on the (100) plane than on the (110) plane; and
etching the oxide layer to remove the oxide layer from the (110) plane and form a hydrogen-terminated silicon surface thereon;
anisotropically wet etching the (100) and (110) planes to expand the lower portion of the trench such that an etch rate of the (110) plane is faster than a combined etch rate of the oxide layer and the (100) plane.
19. The method as recited in claim 18, wherein the step of anisotropically wet etching includes the step of anisotropically wet etching by employing ammonium hydroxide.
20. The method as recited in claim 18, wherein the step of anisotropically wet etching includes the step of anisotropically wet etching in a batch process.
21. The method as recited in claim 18, wherein the step of anisotropically wet etching includes the step of expanding the trench to form rectangular-shaped trenches.
22. The method as recited in claim 18, further comprising the step of forming a buried plate electrode adjacent to the trench.