1. A pattern forming method comprising:
forming a lower layer organic film on a processing target substrate;
forming an upper layer resist film containing an inorganic element on the lower layer organic film;
exposing a desired pattern on the upper layer resist film and then performing development processing to form an opening in the upper layer resist film;
supplying a coating forming agent to the upper layer resist film having the opening formed therein to embed and form a coating film in the opening of the upper layer resist film;
thermally contracting the coating film to narrow the opening of the upper layer resist film;
removing the coating film by dry etching processing and subsequently selectively removing the lower layer organic film with the upper layer resist film being used as a mask, thereby collectively processing the coating film and the lower layer organic film.
2. The pattern forming method according to claim 1, wherein the inorganic element contained in the upper layer resist film is silicon (Si).
3. The pattern forming method according to claim 1, wherein the upper layer resist film has dry etching resisting properties higher than those of the lower layer organic film and the coating film.
4. The pattern forming method according to claim 1, wherein the coating forming agent is a water-soluble resin.
5. The pattern forming method according to claim 1, wherein, as a method of supplying the coating forming agent, pure water is supplied to the upper layer resist film subject to the development processing to effect cleaning processing, and subsequently pure water substitutes for the coating forming agent.
6. The pattern forming method according to claim 1, wherein the lower layer organic film is a coating type carbon film.
7. The pattern forming method according to claim 1, wherein the etching resistance of the resist containing the inorganic element is higher than that of the lower layer organic film.
8. The pattern forming method according to claim 1, wherein the upper layer resist film is configured for ArF.
9. A manufacturing method of a semiconductor device which manufactures the semiconductor device, comprising:
forming a lower layer organic film on a processing target substrate;
forming an upper layer resist film containing an inorganic element on the lower layer organic film;
exposing a desired pattern to the upper layer resist film and then performing development processing to form an opening in the upper layer resist film;
supplying a coating forming agent to the upper layer resist film having the opening formed therein to embed and form a coating film in the opening of the upper layer resist film;
thermally contracting the coating film to narrow the opening of the upper layer resist film; and
removing the coating film by dry etching processing and subsequently selectively removing the lower layer organic film with the upper layer resist film being used as a mask, thereby collectively processing the coating film and the lower layer organic film.
10. The manufacturing method of a semiconductor device according to claim 9, wherein the inorganic element contained in the upper layer resist film is silicon (Si).
11. The manufacturing method of a semiconductor device according to claim 9, wherein the upper layer resist film has dry etching resisting properties higher than those of the lower layer organic film and the coating film.
12. The manufacturing method of a semiconductor device method according to claim 9, wherein the coating forming agent is a water-soluble resin.
13. The manufacturing method of a semiconductor device according to claim 9, wherein, as a method of supplying the coating forming agent, pure water is supplied to the upper layer resist film subject to the development processing to effect cleaning processing, and subsequently pure water substitutes for the coating forming agent.
14. The manufacturing method of a semiconductor device according to claim 9, wherein the lower layer organic film is a coating type carbon film.
15. The manufacturing method of a semiconductor device according to claim 9, wherein the etching resistance of the resist containing the inorganic element is higher than that of the lower layer organic film.
16. The manufacturing method of a semiconductor device according to claim 9, wherein the upper layer resist film is configured for ArF.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fabricating method of a memory device, the fabricating method comprising:
providing a substrate comprising a first portion and a second portion;
forming a plurality of semiconductor fin structures on the substrate of the first portion, wherein each of the semiconductor fin structures extends in a first direction and comprises a first doped region and a body region on which the first doped region is disposed, and a trench is formed between two adjacent semiconductor fin structures;
forming a second doped region in the substrate under the body regions of the semiconductor fin structures and the trench, wherein the second doped region extends into the substrate of the second portion;
forming a plurality of word lines on the substrate, wherein each of the word lines extends in a second direction and covers a portion of a sidewall and a portion of a top of each of the semiconductor fin structures, and the second direction is different from the first direction;
forming a charge storage layer between the semiconductor fin structures and the word lines;
forming a plurality of first contacts on the second portion of the substrate, wherein the first contacts are arranged in the first direction and each of the first contacts is electrically connected with the second doped region; and
forming a plurality of second contacts on the first portion of the substrate, wherein each of the second contacts is electrically connected with the corresponding first doped region.
2. The fabricating method according to claim 1, wherein a method of forming the semiconductor fin structures comprises:
forming a doped layer on the substrate; and
patterning the doped layer and the substrate to form the semiconductor fin structures.
3. The fabricating method according to claim 2, further comprising:
forming a hard mask layer on the doped layer and forming a patterned mask layer on the hard mask layer before patterning the doped layer and the substrate; and
patterning the hard mask layer, the doped layer, and the substrate with the patterned mask layer as a mask to form a plurality of patterned hard mask layers, the first doped regions, and the body regions.
4. The fabricating method according to claim 3, wherein the hard mask layer comprises an oxide layer and a nitride layer.
5. The fabricating method according to claim 3, wherein a material of the hard mask layer comprises silicon oxide, silicon nitride, an advanced patterning film, or a combination thereof.
6. The fabricating method according to claim 3, wherein a method of forming the second doped region comprises:
performing an ion implantation process on the substrate with the patterned hard mask layers as masks to implant a dopant in the substrate and form the second doped region.
7. The fabricating method according to claim 6, further comprising: performing a thermal annealing process to cause the dopant to form the second doped region.
8. The fabricating method according to claim 7, further comprising: removing the patterned hard mask layers.
9. The fabricating method according to claim 1, wherein the method of forming the semiconductor fin structures comprises:
forming a stack layer on the substrate, wherein the stack layer comprises a first doped layer, a body layer, and a second doped layer in sequence from bottom to top; and
patterning the first doped layer and the body layer to form the semiconductor fin structures, wherein the second doped layer serves as the second doped region.
10. The fabricating method according to claim 9, wherein the stack layer comprises the first doped layer, a first barrier layer, the body layer, a second barrier layer, and the second doped layer in sequence from bottom to top.
11. The fabricating method according to claim 10, wherein a material of the barrier layer comprises oxide, nitride, oxynitride, or a combination thereof.
12. The fabricating method according to claim 1, wherein two bottom corners of each trench are right angles, chamfer angles, or round angles.
13. The fabricating method according to claim 1, further comprising:
forming a plurality of isolation structures in the second portion of the substrate; and
forming a third doped region in the substrate between the isolation structures, wherein the third doped region is electrically connected with the second doped region,
wherein each of the first contacts is electrically connected with the second doped region through the third doped region.
14. The fabricating method according to claim 1, further comprising: forming a plurality of contact holes in the substrate of the second portion, wherein a bottom of each of the contact holes exposes the second doped region, and each of the first contacts is electrically connected with the second doped region at the bottom of the corresponding contact hole.
15. The fabricating method according to claim 1, wherein a material of the charge storage layer comprises silicon oxide, silicon nitride, or a combination thereof.
16. The fabricating method according to claim 1, wherein the second doped region connects each of the semiconductor fin structures.
17. The fabricating method according to claim 1, wherein the first doped region, the second doped region, and the third doped region are a first conductivity type; and the body region is a second conductivity type, wherein the first conductivity type and the second conductivity type are different.