1. A method for partitioning a data block comprising:
determining a first boundary condition for the data block at a first data position using a first algorithm;
determining whether a boundary is needed based on a result of the first algorithm; and
determining the boundary location using a second algorithm if the first algorithm result indicates the boundary is needed.
2. The method of claim 1, wherein the first equation uses a first range of mean subblock length to determining the first boundary condition
3. The method of claim 2, wherein the second equation uses a second range of mean subblock length to determining the second boundary condition
4. The method of claim 2, wherein the first range comprises a range of 0 to 4095.
5. The method of claim 1, wherein the second range is larger than the first range.
6. The method of claim 1, wherein the first equation is represented by: HSPA(b1,b2,b3)=(((b1<<8) xor (b2<<4) xor b3)|p)==v, wherein HSPA is a Boolean function to test for boundary condition, wherein b1, b2, and b3 are bytes preceding the first data position, wherein << is left bit shift and >> is right bit shift, wherein p is a target mean subblock length having a range of 0 to 65535, and wherein v is a constant in the range 0,p\u22121.
7. The method of claim 6, wherein p has a range of 0 to 4095.
8. The method of claim 6, wherein the second equation is represented by: LSPA(c\u221215..0)=((md5(c\u221215..0)|232)|q)=w, wherein md5 is a cryptographic hash algorithm, c15..0 comprises 16 bytes to the left of the first data position, q is a target mean subblock length having a range of 0\u2212232\u22121, and wherein w is a constant in the range 0,q\u22121.
9. The method of claim 1, wherein the first and second equations are executed concurrently.
10. The method of claim 1, wherein the first equation is a high-speed data partitioning algorithm and the second equation is a low-speed data partitioning algorithm.
11. The method of claim 1, wherein the second equation is executed based on a result from the first equation.
12. A computer program product comprising a computer useable medium having computer readable program code functions embedded in the medium for partitioning a data block comprising:
computer readable program code that causes the computer to determine a first boundary condition for the data block at a first data position using a first algorithm
computer readable program code that causes the computer to determine whether a boundary is needed based on a result of the first algorithm;
and
computer readable program code that causes the computer to determine the boundary location using a second algorithm if the first algorithm indicates the boundary is needed.
13. The computer program product of claim 12, further comprising a computer readable program code that causes the computer to use a first range of mean subblock length to determining the first boundary condition
14. The computer program product of claim 12, further comprising a computer readable program code that causes the computer to use a second range of mean subblock length to determining the second boundary condition
15. The computer program product of claim 13, wherein the first range comprises a range of 0 to 4095.
16. The computer program product of claim 15, wherein the second range is larger than the first range.
17. The computer program product of claim 12, wherein the first equation is represented by: HSPA(b1,b2,b3)=(((b1<<8) xor (b2<<4) xor b3)|p)==v, wherein HSPA is a Boolean function to test for boundary condition, wherein b1, b2, and b3 are bytes preceding the first data position, wherein << is left bit shift and >> is right bit shift, wherein p is a target mean subblock length having a range of 0 to 65535, and wherein v is a constant in the range 0,p\u22121.
18. The computer program product of claim 12, wherein the second equation is represented by: LSPA(c\u221215..0)=((md5(c\u221215..0)|232)|q)=w, wherein md5 is a cryptographic hash algorithm, c15..0 comprises 16 bytes to the left of the first data position, q is a target mean subblock length having a range of 0\u2212232\u22121, and wherein w is a constant in the range 0,q\u22121.
19. The computer program product of claim 12, wherein the first and second equations are executed concurrently.
20. The computer program product of claim 12, wherein the second equation is executed based on a result from the first equation.
21. The computer program product of claim 12, wherein the first equation is a high-speed data partitioning algorithm and the second equation is a low-speed data partitioning algorithm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bidirectional shift register comprising:
a plurality of serially connected unit registers in which transfer is controlled by any of three or more clock signals each having a different phase from one another, and a setting signal which determines shift direction; and
a selection circuit which can select at least one clock signal from said three or more clock signals in accordance with said setting signal; wherein
said unit registers are formulated so as to be put in a reset state by one clock signal selected by said selection circuits corresponding to each of said unit registers.
2. The bidirectional shift register according to claim 1, wherein each of said unit registers comprises:
an output terminal;
an output circuit which drives said output terminal;
an input circuit into which an output signal of an adjacent unit register and said setting signal are inputted, and which drives said output circuit to put said output terminal at an active level, based on said output signal and said setting signal; and
a reset transistor which drives said output circuit so as to put said output terminal at an inactive level, by one clock signal selected by said selection circuit.
3. The bidirectional shift register according to claim 2, wherein
said output circuit includes a first output transistor which provides control to put said output terminal at an inactive level; and
said reset transistor is diode-connected, one clock signal selected by said selection circuit being supplied to a drain, and a source being connected to a gate of said first output transistor.
4. The bidirectional shift register according to claim 2, wherein
said output circuit includes a second output transistor which provides control to put said output terminal at an active level;
said input circuit includes a first, a second, and a third input transistor;
said first input transistor is diode-connected, another clock signal selected by said selection circuit being supplied to a drain, and a source being connected to a drain of said second and third input transistors; and
output signals of one and another adjacent unit registers are supplied to respective gates of said second and third input transistors, and sources are commonly connected to a gate of said second output transistor.
5. The bidirectional shift register according to claim 1, wherein
said selection circuit includes a switch element which switches to an ON state or an OFF state according to said setting signal, and
said three or more clock signals are selectively outputted to said unit register(s), by said switch element.
6. A bidirectional shift register comprising:
a plurality of serially connected unit registers in which transfer is controlled by any of three or more clock signals each having a different phase from one another, and a setting signal which determines shift direction; and
a selection circuit which can select at least one clock signal from said three or more clock signals in accordance with said setting signal; wherein
said unit registers are formulated so as to be put in a reset state by one clock signal selected by said selection circuit, corresponding to each of said unit registers;
said selection circuit comprises at least a first selection transistor and a second selection transistor;
in said first selection transistor, wiring for any of said three or more clock signals is connected to a gate electrode and a source electrode, and a drain electrode is connected to a source electrode of said second selection transistor; and
in said second selection transistor, wiring for said setting signal is connected to a gate electrode, and said selected one clock signal is outputted from a drain electrode.
7. The bidirectional shift register according to claim 6, wherein
said first selection transistor is controlled to an ON state or an OFF state by any of said three or more clock signals; and
said second selection transistor is controlled to an ON state or an OFF state by said setting signal.
8. The bidirectional shift register according to claim 6, wherein each of said unit registers comprises:
an output terminal;
an output circuit which drives said output terminal; and
an input circuit into which an output signal of an adjacent unit register and said setting signal are inputted, and which drives said output circuit to put said output terminal at an active level, based on said output signal and said setting signal; and wherein
said output circuit includes a first output transistor in which one clock signal selected by said selection circuit is supplied to a gate to perform control to put said output terminal at an inactive level.
9. The bidirectional shift register according to claim 8, wherein
said output circuit includes a second output transistor which performs control to put said output terminal at an active level;
said input circuit includes first and said second input transistors;
with regard to said first and said second input transistors, a drain of one of said first and said second input transistors selected by said setting signal is supplied with another clock signal selected by said selection circuit, output signals of one and another adjacent unit registers are supplied to respective gates, and sources are commonly connected to a gate of said second output transistor.
10. A bidirectional shift register according to claim 1, wherein
said selection circuit is provided for all of said plurality of unit registers, or per a prescribed number of said unit registers.
11. A display device comprising a pixel array in which a plurality of pixels is arrayed, and a scanning circuit which makes said pixels active, wherein said scanning circuit includes said bidirectional shift register according to claim 1.
12. The display device according to claim 11, wherein transistors included in said bidirectional shift register and switch transistors in said pixels comprise only one of either NMOS transistors or PMOS transistors.
13. The display device according to claim 11, wherein scanning circuits are provided on each of both sides of a layout region of said pixel array.
14. The display device according to claim 13, wherein said scanning circuits provided on each of both sides of said layout region of said pixel array drive a gate of an identical switch transistor at the same time.