1. A semiconductor device, comprising:
a first MISFET including a first gate formed over a principal surface of a semiconductor substrate through a first insulating film;
a second MISFET including a second gate which is thicker than the first gate, formed over the principal surface of the semiconductor substrate through a second insulating film which is thicker than the first gate insulating film; and
a memory cell including a control gate formed over the principal surface of the semiconductor substrate through a third gate insulating film, a charge storage layer in which one part thereof is formed at one sidewall of the control gate as well as the other part thereof is formed over the principal surface of the semiconductor substrate, and a memory gate which is electrically separated from the control gate through the one part of the charge storage layer, as well as electrically separated from the semiconductor substrate through the other part of the charge storage layer, forming a split gate together with the gate control gate, and
wherein the third gate insulating film is thinner than the second gate insulating film, the control gate is thicker than the first gate and the ratio of height of the memory gate with respect to the gate length of the memory gate is larger than 1.
2. The semiconductor device according to claim 1,
wherein the third gate insulating film is formed with the first gate insulating film by oxidizing the principal surface of the semiconductor substrate.
3. The semiconductor device according to claim 1,
wherein the control gate and the second gate are formed in a multilayer structure including a first electrode material film and a second electrode material film formed over the first electrode material film, and
wherein the first gate is a single layer structure including a first electrode material film of the control gate.
4. The semiconductor device according to claim 1,
wherein the memory cell further includes a first semiconductor region formed over the principal surface of the semiconductor substrate by ion implantation of a first impurity, using the split gate as a mask, a sidewall formed at the other sidewall of the control gate as well as formed at a sidewall of the opposite side of the one side of the charge storage layer in the memory gate, and a second semiconductor region formed over the principal surface of the semiconductor substrate by ion implantation of a second impurity, using the split gate and the sidewall as masks, which has higher impurity concentration than the first semiconductor region.
5. The semiconductor device according to claim 4,
wherein the semiconductor substrate is made of a silicon substrate,
wherein the memory cell further includes a spacer formed at the sidewall of the split gate through the sidewall and a silicide layer formed over the second semiconductor region, one end of which is arranged in the vicinity of the spacer, and
wherein the silicide layer is not formed in the first semiconductor region.
6-11. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic system, comprising:
an integrated circuit disposed on a first side of a substrate;
a via formed through the first side of the substrate to a backside of the substrate;
a recess in the backside of the substrate, wherein the recess comprises an elongate path formed in the substrate;
insulating material disposed in and filling the recess in the backside of the substrate to an edge of the recess, wherein the insulating material is at least partially covered by a trace formed on the backside of the substrate, wherein the trace comprises a thin piece of conductive material that follows the elongate path and is positioned within the boundaries of the elongate path.
2. The system of claim 1, comprising an image sensor coupled to the substrate.
3. The system of claim 1, comprising a buffer zone between an edge of the trace and an edge of the insulating material, wherein the buffer zone includes a portion of the insulating material that is not covered by the trace.
4. The system of claim 1, comprising a passivation layer disposed over the trace opposite the insulating material.
5. The system of claim 1, wherein the trace comprises under-bump-metallurgy features disposed thereon.
6. An electronic system, comprising:
an integrated circuit disposed on a first side of a substrate;
a via formed through the first side of the substrate to a backside of the substrate; and
insulating material disposed in and filling a recess in the backside of the substrate to an edge of the recess, wherein the insulating material is at least partially covered by a trace formed on the backside of the substrate, wherein the recess comprises a trench that contains the insulating material within boundaries of the trench.
7. The system of claim 6, wherein the trace is positioned within boundaries of the insulating material such that a buffer zone is formed between an edge of the trace and an edge of the insulation material.
8. A semiconductor device, comprising:
a substrate;
an elongate recess in one side of the substrate;
insulation disposed in the elongate recess such that the elongate recess is filled with the insulation; and
a conductive layer disposed over the insulation such that the conductive layer remains within boundaries defined by the elongate recess and portions of the insulation are not covered by the conductive layer.
9. The semiconductor device of claim 8, comprising a via formed through the substrate.
10. The semiconductor device of claim 9, wherein the conductive layer comprises a trace.
11. The semiconductor device of claim 8, comprising an integrated circuit coupled to a side of the substrate opposite the elongate recess.
12. An electronic system, comprising:
a substrate comprising a front side and a back side;
a trench formed on a backside of the substrate, wherein the trench comprises an elongate path;
an insulating material disposed within and contained by the trench such that the insulating material fills the trench to an edge of the trench; and
a trace at least partially covering the insulating material, wherein the trace comprises conductive material that follows the elongate path within boundaries of the trench.
13. The system of claim 12, comprising a via formed in the substrate.
14. The system of claim 12, wherein the substrate comprises a semiconductor wafer.
15. The system of claim 12, comprising an image sensor.
16. The system of claim 12, comprising an integrated circuit die coupled with the substrate.
17. The system of claim 12, comprising under-bump-metallurgy features disposed on the trace.