1. A tamperproof genuineness ID device with self-destruct protection function, wherein the tamperproof genuineness ID device comprising a working part with self-destruct protection function and an detecting work part for processing data;
wherein the tamperproof genuineness ID device and a product to be detected are airtight sealed or fixed together, and the a working part with self-destruct protection function are arranged in the airtight sealed or fixed state of the tamperproof genuineness ID device and the product to be detected; and
the detecting work part comprises a data input interface, the detecting work part reads information data from an out-built tamper-resistant medium via the data input interface wherein, the built-out tamper-resistant medium is a tamper-resistant card, the tamper-resistant card is stored with random information data, and a tamperproof genuineness ID code unique for the tamper-resistant medium is hidden in the random information data;
the tamperproof genuineness ID device and the product to be detected are integrated together by means of sealing in a carrier via decompressing or pressurizing;
the working part with self-destruct protection function comprises a working part with pressure change self-destruct protection function or a working part with breakage self-destruct protection function, wherein the working part with pressure change self-destruct protection is triggered by pressure change in the sealed carrier;
the tamperproof genuineness ID device including the working part with pressure change self-destruct protection function is separated into a first working chamber and a second working chamber by a middle diaphragm which extends or shrinks in response to pressure change;
wherein the first working chamber communicates with outside atmosphere, the second working chamber communicates with a carrier which accommodates the product to be detected; wherein the middle diaphragm is extended or shrunk by pressure changed in the second working chamber, so as to trigger the working part with pressure change self-destruct protection function.
2. The tamperproof genuineness ID device as claimed in claim 1, wherein the detecting work part comprises a device for displaying or broadcasting a detecting result.
3. The tamperproof genuineness ID device as claimed in claim 1, wherein the working part with breakage self-destruct protection function is triggered by the change of relative position between the tamperproof genuineness ID device and the product to be detected.
4. The tamperproof genuineness ID device as claimed in claim 3, wherein the tamperproof genuineness ID device including the working part with breakage self-destruct protection function comprises magnetic substance which keeps a magnetic balance with the magnetic substance in the product to be detected, and the tamperproof genuineness ID device and the product to be detected are fixed together, wherein there is a magnetic switch disposed between the two magnetic substances, and the magnetic switch is controlled by the change of the magnetic balance to switch, so as to control the triggering of the working part with breakage self-destruct protection function.
5. The tamperproof genuineness ID device as claimed in claim 1, wherein the detecting work part comprises:
a microprocessor for reading, identifying, and encrypting a tamperproof genuineness ID code of the tamper-resistant medium according to preset rule;
the working part with self-destruct protection function comprises:
a self-destruct protection circuit to perform self-destruct protection for the microprocessor; and
a self-destruct trigger circuit for controlling the self-destruct protection circuit; and
the tamperproof genuineness ID device further comprises:
a power source for supplying power to the above circuits.
6. The tamperproof genuineness ID device as claimed in claim 5, wherein output terminals of the self-destruct trigger circuit are connected to a control signal input terminal of the self-destruct protection circuit, the self-destruct trigger circuit comprises at least one of a packaging breakage trigger circuit, a magnetic balance breaking trigger circuit, a photosensitive trigger circuit, a disassemble trigger circuit, an insufficient voltage trigger circuit, and a using tries limited trigger circuit;
wherein the input terminal of the packaging breakage trigger circuit is connected with a packaging breakage trigger unit;
the input terminal of the magnetic balance breaking trigger circuit is connected with a magnetic balance sensor;
the input of the photosensitive trigger circuit is connected with a photosensor;
the input of the disassemble trigger circuit is connected with an disassemble trigger unit;
the insufficient voltage trigger circuit has an input terminal connected to a output terminal of a power source; and
the using tries limited trigger circuit has an input terminal connected to a using tries limited output terminal of the microprocessor.
7. The tamperproof genuineness ID device as claimed in claim 5, wherein the self-destruct protection circuit is a self-destruct voltage booster circuit or a storedregistered information deleted circuit.
8. A tamperproof genuineness ID method with self-destruct function by employing the tamperproof genuineness ID device with self-destruct protection function according to claim 1, wherein, the tamperproof genuineness ID method comprises the steps of:
A. setting the tamper-resistant medium in a coordinate working state with the tamperproof genuineness ID device;
B. identifying and alining the tamperproof genuineness ID code from random information code in the tamper-resistant medium by the detecting work part of the tamperproof genuineness ID device which operates according to preset programs and instructions, and performing encryption and calculation to the tamperproof genuineness ID code to get the native genuineness ID code; and
C. outputting a detecting result.
9. The tamperproof genuineness ID method as claimed in claim 8, wherein the step A comprises the steps of:
A1. determining whether the product to be detected and the tamperproof genuineness ID device are in an effective working state;
A2. setting the tamper-resistant medium in a coordinate working state with the tamperproof genuineness ID device; and
A3. pressing an on-off button set on the tamperproof genuineness ID device to activate the tamperproof genuineness ID device.
10. The tamperproof genuineness ID method as claimed in claim 9, wherein the step B comprises the steps of:
B1. reading, identifying and arranging a tamperproof genuineness ID code from the tamper-resistant medium by the microprocessor of the tamperproof genuineness ID device which operates according to preset programs and instructions;
B2. performing encryption and calculation on the tamperproof genuineness ID code by the microprocessor which operates according to preset programs, instructions and encrypting key, so as to get the native genuineness ID code;
B3. decoding the native genuineness ID code to get a converted native genuineness ID code and displaying on a display device; and
B4. determining whether the converted native genuineness ID code is identical with a preset native genuineness ID code which is unique to the tamper-resistant medium.
11. The tamperproof genuineness ID method as claimed in claim 8, wherein the step C comprises display outputting andor audio outputting.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor apparatus comprising:
a command control unit configured to decode external signals and generate a read strobe signal, a write strobe signal, a read command, and a write command;
a clock enable signal generation unit configured to generate a read clock enable signal in response to the read strobe signal and generate a write clock enable signal in response to the write strobe signal;
a clock control unit configured to generate a first control clock signal and a second clock control signal in response to an internal clock signal, the read clock enable signal, and the write clock enable signal; and
is a latency shift unit configured to generate a first latency signal in response to a delayed read command and the first control clock signal and generate a second latency signal in response to a delayed write command and the second control clock signal.
2. The semiconductor apparatus according to claim 1, further comprising:
a delay locked loop (DLL) configured to receive an external clock signal and generate the internal clock signal for compensating for an internal signal processing delay time of the semiconductor apparatus.
3. The semiconductor apparatus according to claim 2, further comprising:
a delay unit configured to delay the read command and the write command by a predetermined delay time and output the delayed read command and the delayed write command.
4. The semiconductor apparatus according to claim 3, wherein the predetermined delay time is adjusted to the same value as a delay time which is internally adjusted in the DLL.
5. The semiconductor apparatus according to claim 1, wherein the external signals comprise a column address strobe signal, a row address strobe signal, and a write enable signal.
6. The semiconductor apparatus according to claim 1, wherein the command control unit comprises:
a command decoder configured to decode the external signals and generate an active command, the read command, and the write command;
a first logic circuit configured to combine the active command, the column address strobe signal, and the inverted write enable signal and generate the read strobe signal; and
a second logic circuit configured to combine the active command, the column address strobe signal, and the write enable signal and generate the write strobe signal.
7. The semiconductor apparatus according to claim 1, wherein the clock enable signal generation unit is configured to generate the read clock enable signal in response to the read strobe signal and a read period signal and generate the write clock enable signal in response to the write strobe signal and a write period signal.
8. The semiconductor apparatus according to claim 7, wherein the latency shift unit is configured to generate the first latency signal and the read period signal in response to the delayed read command and the first control clock signal, and generate the second latency signal and the write period signal in response to the delayed write command and the second control clock signal.
9. The semiconductor apparatus according to claim 1, further comprising:
a transmission unit configured to perform a data driving operation corresponding to the read command; and
a termination control unit configured to control termination of the transmission unit during read and write operations of the semiconductor apparatus, in response to the first control clock signal, the first latency signal, and the second latency signal.
10. The semiconductor apparatus according to claim 9, wherein the termination control unit is configured to control on-die termination of the transmission unit in response to the first control clock signal and the first latency signal, during the read operation of the semiconductor apparatus.
11. The semiconductor apparatus according to claim 9, wherein the termination control unit is configured to dynamic on-die termination of the transmission unit in response to the second latency signal, during the write operation of the semiconductor apparatus.
12. The semiconductor apparatus according to claim 1, wherein the clock enable signal generation unit comprises:
a first signal generator configured to generate the read clock enable signal in response to the read strobe signal and a read period signal; and
a second signal generator configured to generate the write clock enable signal in response to the write strobe signal and a write period signal.
13. The semiconductor apparatus according to claim 12, wherein the first signal generator comprises:
a flip-flop array;
a latch configured to set an output signal thereof in response to the read strobe signal and reset the output signal after a delay time by the flip-flop array; and
a logic circuit configured to combine the output signal of the latch and the read period signal and generate the read clock enable signal.
14. The semiconductor apparatus according to claim 12, wherein the second signal generator comprises:
a flip-flop array;
a latch configured to set an output signal thereof in response to the write strobe signal and reset the output signal after a delay time by the flip-flop array; and
a logic circuit configured to combine the output signal of the latch and the write period signal and generate the write clock enable signal.
15. The semiconductor apparatus according to claim 1, wherein the command control unit is configured to active only the read strobe signal between the read strobe signal and the write strobe signal during the read operation of the semiconductor apparatus.
16. The semiconductor apparatus according to claim 15, wherein the clock control unit is configured to output a clock signal, which corresponds to an activation period of the read clock enable signal in the internal clock signal, as the first control clock signal during the read operation of the semiconductor apparatus.
17. The semiconductor apparatus according to claim 1, wherein the command control unit is configured to activate only the write strobe signal between the read strobe signal and the write strobe signal during the write operation of the semiconductor apparatus.
18. The semiconductor apparatus according to claim 17, wherein the clock control unit is configured to output a clock signal, which corresponds to an activation period of the write clock enable signal in the internal clock signal, as the second control clock signal during the write operation of the semiconductor apparatus.