1-10. (canceled)
11. An alkyl ether sulfate salt of the general formula I
RO\u2014(CH2\u2014CHR1O)y\u2014(CH2CH2O)zSO3\u2212M+\u2003\u2003(I),
wherein
R is an unbranched or branched C10-C15-alkyl radical or mixtures of different unbranched or branched C10-C15-alkyl radicals,
R1 is methyl,
M+ is a cation, selected from the group consisting of alkali metals, NH4+ and HNR23+, where R2 is selected from the group consisting of unbranched or branched alkyl radicals, CH2CH2OH and CH2CH(OH)CH3,
y has a mean value of 1-2, and
z has a mean value of 1-4,
for which the quotient A of the critical micelle concentration (cmc)
A
=
c
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RO
–
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z
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+
)
c
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RO
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>
1.
12. The method of using as an anion surfactant component in laundry detergents and cleaning compositions the alkyl ether sulfate salts as claimed in claim 11.
13. The method as claimed in claim 12, wherein said laundry detergents and cleaning compositions are selected from the group consisting of powder laundry detergents, compact laundry detergents, super compact laundry detergents, laundry detergent extrudates, laundry detergent gels, liquid laundry detergents, liquid laundry detergent pouches, liquid laundry detergent concentrates, hand dishwashing detergents, dishwashing detergents for mechanical dishwashers, scouring cleaners or scouring milk, handwashing pastes or gels, all-purpose cleaners, glass cleaners, window cleaners, floor cleaners, bath cleaners, WC cleaners, kitchen cleaners, slaughterhouse cleaners, car shampoos and metal cleaners.
14. The method of using as an anion surfactant component in chemical engineering applications the alkyl ether sulfate salts as claimed in claim 11.
15. The method as claimed in claim 14, wherein said chemical engineering applications are selected from the group consisting of textile aids, papermaking aids and leather aids, fire-extinguishing foams, pesticide formulations, uses in emulsion polymerizations, for metal pretreatment, as aids for the ceramics industry, as cooling lubricants and in emulsifying processes.
16. The method of using in cosmetics applications the alkyl ether sulfate salts as claimed in claim 11.
17. The method as claimed in claim 16, wherein said cosmetics applications are selected from the group consisting of shower gels, hair shampoos, bath additives, syndets, lotions, oilsperfume oils, liquid handwashing soaps and emulsifiers for creams.
18. A laundry detergent or cleaning composition or cosmetics formulation comprising an alkyl ether sulfate salt as claimed in claim 11.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor storage device comprising:
a memory cell configured to store data;
a bit line associated with a potential, wherein the potential changes based on write data to be written to the memory cell;
a precharge circuit configured to precharge the bit line; and
a precharge control circuit configured to control precharging of the bit line based on the potential of the bit line and the write data,
wherein the precharge circuit comprises a precharge transistor, a source of the precharge transistor connected to a power supply potential and a drain of the precharge transistor connected to the bit line, and
wherein the precharge control circuit is further configured to provide a local precharge signal to a gate of the precharge transistor.
2. A semiconductor storage device, comprising:
a memory cell configured to store data;
a bit line associated with a potential, wherein the potential changes based on write data to be written to the memory cell;
a precharge circuit configured to precharge the bit line; and
a precharge control circuit configured to control precharging of the bit line based on the potential of the bit line and the write data, wherein, when a potential of the bit line based on the write data is equal to a potential of the bit line before being precharged, the write data is written to the memory cell without precharging the bit line.
3. A semiconductor storage device, comprising:
a memory cell configured to store data;
a bit line associated with a potential, wherein the potential changes based on write data to be written to the memory cell;
a precharge circuit configured to precharge the bit line; and
a precharge control circuit configured to control precharging of the bit line based on the potential of the bit line and the write data; and
a write amplifier configured to drive the bit line based on the write data at a time of writing.
4. The semiconductor storage device according to claim 3, further comprising a column selector configured to select memory cells for each column of a memory cell array.
5. The semiconductor storage device according to claim 4, wherein the column selector comprises a select transistor that is connected in series with the bit line and is configured to receive a column select signal at a gate of the select transistor.
6. The semiconductor storage device according to claim 3, wherein the write amplifier comprises a write transistor connected in series with the select transistor and a NOR circuit, the NOR circuit configured to drive a gate of the write transistor based on a logical NOR of the write data and a write enable signal.
7. The semiconductor storage device according to claim 5, wherein, when a potential of the bit line based on the write data is equal to a potential of the bit line before being precharged and a precharge signal is issued at a time of writing, the write data is written to the memory cell without precharging a bit line of a selected column.
8. The semiconductor storage device according to claim 1, wherein a plurality of memory cells are arranged in a matrix comprising a row direction and a column direction.
9. The semiconductor storage device according to claim 8, further comprising:
a row decoder configured to perform row selection of the memory cell; and
a word line configured to drive a memory cell in a row selected by the row decoder.
10. The semiconductor storage device according to claim 9, wherein the memory cell comprises an SRAM.
11. The semiconductor storage device according to claim 10, wherein the memory cell comprises:
a first CMOS inverter comprising a first drive transistor and a first load transistor connected in series,
a second CMOS inverter comprising a second drive transistor and a second load transistor connected in series,
a first transfer transistor connected between a first storage node provided at a connection point of the first drive transistor and the first load transistor and a first bit line, and
a second transfer transistor connected between a second storage node provided at a connection point of the second drive transistor and the second load transistor and a second bit line;
wherein an output and an input of the first CMOS inverter and the second CMOS inverter are cross-coupled with each other, and
wherein a gate of the first transfer transistor and a gate of the second transfer transistor are connected to the word line.
12. The semiconductor storage device according to claim 1, further comprising a sense amplifier configured to detect data stored at the memory cell based on a signal read out from the memory cell on the bit line.
13. The semiconductor storage device according to claim 1, wherein when a read operation or a write operation is not performed, the bit line is maintained in a floating state.
14. A semiconductor storage device, comprising:
a memory cell configured to store data;
a bit line associated with a potential, wherein the potential changes based on write data to be written to the memory cell;
a precharge circuit configured to precharge the bit line; and
a precharge control circuit configured to control precharging of the bit line based on the potential of the bit line and the write data,
wherein the precharge control circuit comprises:
an EXOR circuit configured to receive a potential of the bit line and the write data,
a NAND circuit configured to receive an output of the EXOR circuit, a write enable signal, and a column select signal,
a NOR circuit configured to receive an output of the NAND circuit and a global precharge signal, and
an inverter configured to generate a local precharge signal by inverting an output of the NOR circuit and outputting the local precharge signal to the precharge circuit.
15. The semiconductor storage device according to claim 14, wherein, when a logical value of the global precharge signal is \u20181\u2019, a logical value of the local precharge signal is set to \u20181\u2019 and precharge of the bit line is not performed.
16. The semiconductor storage device according to claim 14, wherein, when logical values of the global precharge signal and the write enable signal are \u20180\u2019, a logical value of the local precharge signal is set to \u20180\u2019 and precharge of the bit line is performed.
17. The semiconductor storage device according to claim 14, wherein, when logical values of the global precharge signal and the column select signal are \u20180\u2019 and a logical value of the write enable signal is \u20181\u2019, a logical value of the local precharge signal is set to \u20180\u2019 and precharge of the bit line is performed.
18. The semiconductor storage device according to claim 14, wherein, when a logical value of the global precharge signal is \u20180\u2019 and logical values of the write enable signal and the column select signal are \u20181\u2019, if a potential of the bit line is equal to the write data, a logical value of the local precharge signal is set to \u20181\u2019 and precharge of the bit line is not performed.
19. The semiconductor storage device according to claim 14, wherein, when a logical value of the global precharge signal \u20180\u2019 and logical values of the write enable signal and the column select signal are \u20181\u2019, if a potential of the bit line is different from the write data, a logical value of the local precharge signal is set to \u20180\u2019 and precharge of the bit line is performed.