1. A device operable to transfer an input signal between differently referenced circuits, comprising:
an input circuit referenced to a first voltage reference and operable to provide the input signal;
a receiving device coupled to receive the input signal from the input circuit;
a biasing circuit coupled to the receiving device to provide a biasing voltage reference for the receiving device;
a first level shifter coupled to the input circuit and the receiving device for translating the input signal so it is referenced to the bias voltage;
an output circuit referenced to a second voltage reference; and
a second level shifter coupled to receive the translated input signal and to provide the translated input signal to the output circuit,
whereby an output signal is provided which is related to the input signal and referenced to the second voltage reference.
2. A device according to claim 1, wherein the first reference voltage is a stable logic ground, and the second reference voltage is a floating ground.
3. A device according to claim 1, wherein the first reference voltage is a floating ground, and the second reference voltage is a stable logic ground.
4. A device according to claim 1, wherein the input and output circuits are adapted to operate at voltages which are substantially different in magnitude.
5. A device according to claim 1, wherein the device is implemented in an integrated circuit, and further includes:
a first voltage isolation structure around the input circuit capable of withstanding a voltage level which exceeds the operating voltage of the input circuit; and
a second voltage isolation structure around the output circuit capable of withstanding a voltage level which exceeds the operating voltage of the output circuit.
6. A device according to claim 4, wherein the magnitude of the isolation voltage level for the input circuit is lower than the magnitude of the isolation voltage level for the output circuit.
7. A device according to claim 6, wherein the first reference voltage is a stable logic ground, the second reference voltage is a floating ground, and the bias voltage in negative relative to the stable ground.
8. A device according to claim 5, wherein the first reference voltage is a floating ground, the second reference voltage is a stable logic ground, and the bias voltage is negative relative to the stable ground.
9. A device according to claim 1 wherein the input circuit is operative to convert a current sense signal level to a pulse interval signal.
10. A device operable to transfer input signals between differently referenced circuits, comprising:
an input circuit referenced to a first voltage reference and operable to provide at least one input signal;
respective receiving devices coupled to receive each input signal from the input circuit;
a biasing circuit coupled to the receiving devices to provide a biasing voltage reference for the receiving devices;
respective first level shifters coupled to the input circuit and the receiving devices for translating the input signals so they are referenced to the bias voltage;
one or more output circuits referenced to a respective voltage reference for each input signal; and
respective second level shifters coupled to receive the translated input signals and to provide the translated input signals to the respective output circuits,
whereby output signals are provided which are related to the input signals and referenced to the respective second voltage references.
11. A device according to claim 10, wherein the reference voltage for the input circuit is a stable logic ground, and the output circuit voltage references are floating grounds.
12. A device according to claim 10, wherein the input and output circuits are adapted to operate at voltages which are substantially different in magnitude.
13. A device according to claim 10, wherein the device is implemented in an integrated circuit having a substrate, and the biasing circuit is coupled to the first voltage reference and the substrate to bias the substrate relative to the first voltage reference.
14. A device according to claim 13, wherein the biasing circuit produces a negative voltage bias on the substrate with respect to the first voltage reference.
15. A device according to claim 12, further including:
a first voltage isolation structure around the input circuit capable of withstanding a voltage level which exceeds the input stage operating voltage; and
respective voltage isolation structures around each of the output circuits capable of withstanding voltage level which exceeds the operating voltages of the respective output circuits.
16. A device according to claim 15, wherein the magnitude of isolation voltage for the input circuit is lower than the magnitude of the isolation voltage for at least one of the output circuits.
17. A device according to claim 16, wherein the reference voltage in the input circuit is a stable logic ground; the reference voltages for the output circuits are floating grounds; and the bias voltage is negative relative to the stable ground.
18. A device according to claim 10, further comprising a pulse generator in the input stage and coupled to the input signal,
the pulse generator being operative to output pulses to the level shifting circuit with a pulse duration related to a value of the input signal.
19. A device according to claim 10, including first and second output stages which are low and high drivers for a half bridge switching circuit.
20. A method for transferring an input signal from an input circuit referenced to a first voltage reference to an output circuit referenced to a second voltage reference, the method comprising the steps of:
providing a receiving device biased to a voltage below the first voltage reference;
coupling the input circuit through a first level shifter to the receiving device so that the input signal becomes referenced to the bias voltage reference;
transferring the input signal from the receiving device through a second level shifter to the output circuit whereby the transferred signal is referenced to the second voltage reference level; and
outputting the signal from the output circuit.
21. A method according to claim 20, further comprising isolating the input and output circuits from voltage levels exceeding respective operating voltages for the input and output circuits.
22. The method according to claim 21, further comprising codifying the input signal as an interval between pulses transferred between the input circuit and the output circuit.
23. The method according to claim 20, wherein the voltage biasing the receiving device is lower than the first or second voltage reference levels.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A flash analog-to-digital converter, comprising:
a flash comparator portion to compare an input signal to 2N\u22121 reference voltages and to generate 2N\u22121 corresponding binary valued comparison signals, wherein adjacent comparison signals represent a given least significant bit quantization level;
a time interpolating encoder to detect a difference in arrival time between a first comparison signal and a second comparison signal from among the binary valued comparison signals and, based on the difference, to generate a voltage interpolation signal capable of encoding a plurality of bins within the given least significant bit quantization level, and capable of identifying which of the bins corresponds to the input signal, wherein the time interpolating decoder includes at least one variable delay unit to delay, based on a feedback control signal, at least one of the first comparison signal and the second comparison signal prior to detecting said difference;
a decoder to generate M-bit output data representing an M-bit quantization of the input signal, wherein M is an integer greater than N, based on the binary valued comparison signals and the voltage interpolation signal;
a feedback control signal generator to generate the feedback control signal, the generator including a code density detector to detect a non-uniformity of a code density of the M-bit output data, wherein the generator generates the control signal based on the detecting.
2. The flash analog-to-digital converter of claim 1, wherein the time interpolating encoder varies the width of the bins based on the delay of the variable delay unit.
3. The flash analog-to-digital converter of claim 1, wherein the decoder generates N bits of the M-bit output data based on the 2N\u22121 corresponding binary valued comparison signals and K bits of the M-bit output data are based on the voltage interpolation signal, wherein each of the K bits represents a sub-quantization level smaller that said given least significant bit quantization level.
4. The flash analog-to-digital converter of claim 3,
wherein there are 2K of said bins within said given least significant bit quantization level,
wherein said K bits are capable of encoding 2K states of said 2K bins,
wherein the feedback control signal generator code density detector includes a counter for counting the uniformity of occurrences among all of the states capable of being represented by the K bits and generating a corresponding counting result, and
wherein the generator generates the control signal based on said counting result.
5. The flash analog-to-digital converter of claim 1,
wherein said flash comparator portion includes a first signal level comparator to compare, in response to a sample clock, the input signal to a first reference voltage and to generate a corresponding first comparison signal at a first delay time, the first delay time indicative of the difference between the input signal and the first reference voltage, and includes a second signal level comparator to compare, in response to the sample clock, the input signal to a second reference voltage and to generate a corresponding second comparison signal at a second delay time, the second delay time indicative of the difference between the input signal and the second reference voltage,
wherein the time interpolating encoder includes a first time of arrival detector to detect the difference between the first delay time and the second delay time and to generate, based on said detected difference, a first voltage interpolation signal of said voltage interpolation signals, said first voltage interpolation signal having a binary state representing a sub-quantization level one half of said least significant bit quantization level.
6. The flash analog-to-digital converter of claim 5, wherein said second signal level comparator is capable of outputting a negative second comparison signal substantially concurrent with said second comparison signal, and
wherein said time interpolating encoder further comprises:
a controllable first delay unit to receive the feedback control signal and the negative second comparison signal and to generate a delayed negative second comparison signal, having a delay relative to said negative second comparison signal based on said delay control signal, and
a second time of arrival detector to detect the difference between the first delay time and an occurrence of the delayed negative second comparison signal, to generate, based on said detected difference, a second voltage interpolation signal of said voltage interpolation signals, said second voltage interpolation signal having a binary state representing a first and a second of a plurality of sub-bins within said second quantization level, each of said sub-bins representing approximately one half of said sub-quantization level.
7. The flash analog-to-digital converter of claim 6, wherein said time interpolating encoder further comprises:
a controllable second delay unit to receive the feedback control signal and the first comparison signal and to generate a delayed first comparison signal, having a delay relative to said first comparison signal based on said delay control signal, and
a third time of arrival detector to detect the difference between the second delay time and an occurrence of the delayed first comparison signal to generate, based on said detected difference a third voltage interpolation signal of said voltage interpolation signals, said third voltage interpolation signal representing a third and a fourth of said sub-bins.
8. The flash analog-to-digital converter of claim 3, further comprising:
a multi-level feedback control signal generator for generating, based on said feedback control signal, 2K\u22121\u22121 lower level feedback control signals, and
wherein said flash comparator portion includes a first signal level comparator to compare, in response to a sample clock, the input signal to a first reference voltage and to generate a corresponding first comparison signal at a first delay time, the first delay time indicative of the difference between the input signal and the first reference voltage, and includes a second signal level comparator to compare, in response to the sample clock, the input signal to a second reference voltage and to generate a corresponding second comparison signal at a second delay time, the second delay time indicative of the difference between the input signal and the second reference voltage,
wherein the time interpolating encoder includes
a first controllable delay for concurrently generating 2K\u22121\u22121 different delays of said first comparison signal, based on said 2K\u22121\u22121 lower level feedback control signals,
a second controllable delay for concurrently generating 2K\u22121\u22121 different delays of said second comparison signal, based on said 2K\u22121\u22121 lower level feedback control signals,
a multi-level delay time of arrival detector to detect a difference between the first delay time and the second delay time, to detect a difference between the first delay time and a respective occurrence of each of said 2K\u22121\u22121 different delays of said second comparison signal, and to detect a difference between the second delay time and a respective occurrence of each of said 2K\u22121\u22121 different delays of said first comparison signal, and based on said detecting, to generate 2K\u22121 voltage interpolation signals,
wherein said first comparison signal, said second comparison signal, and said 2K\u22121 voltage interpolation signals represent 2K bins within said least significant bit quantization level.
9. A flash analog-to-digital converting method, comprising:
comparing an input signal to 2N\u22121 reference voltages;
generating 2N\u22121 corresponding binary valued comparison signals, based on the comparing, wherein adjacent comparison signals represent a given least significant bit quantization level;
detecting a difference in arrival time between a first comparison signal and a second comparison signal from among the binary valued comparison signals and, based on the difference, generating a first-to-arrive signal, wherein the detecting includes delaying at least one of the first comparison signal and the second comparison signal prior to detecting said difference;
generating a voltage interpolation signal capable of encoding a plurality of bins within the given least significant bit quantization level, and capable of identifying which of the bins corresponds to the input signal, said generating based on said first-to-arrive signal;
generating an M-bit output data representing an M-bit quantization of the input signal, based on the binary valued comparison signals and the voltage interpolation signal;
detecting a non-uniformity of a code density of the M-bit output data and generating a corresponding uniformity error data;
generating a feedback control signal based on the uniformity error data; and
varying said delaying based on said feedback control signal.
10. The flash analog-to-digital converting method of claim 9, wherein said generating a voltage interpolation signal generates said feedback control signal to vary the width of the bins based on the said delay.
11. The flash analog-to-digital converting method of claim 9, wherein said generating an M-bit output data generates K bits of the M-bit output data based on the voltage interpolation signal.
12. The flash analog-to-digital converting method of claim 11,
wherein there are 2K of said bins within said given least significant bit quantization level,
wherein said K bits are capable of encoding 2K states of said 2K bins,
wherein said code density detecting includes counting the uniformity of occurrences among all of the states capable of being represented by the K bits and generating a corresponding counting result, and
wherein said generating the control signal is based on said counting result.
13. The flash analog-to-digital converting method of claim 9,
wherein comparing the input signal to 2N\u22121 reference voltages includes comparing, in response to a sample clock, the input signal to a first reference voltage, and generating, based on said comparing, a corresponding first comparison signal at a first delay time, the first delay time indicative of the difference between the input signal and the first reference voltage,
comparing, in response to the sample clock, the input signal to a second reference voltage and to generating, based on said comparing, a corresponding second comparison signal at a second delay time, the second delay time indicative of the difference between the input signal and the second reference voltage,
wherein the time interpolating encoding includes detecting the difference between the first delay time and the second delay time, and
generating, based on said detected difference, a first voltage interpolation signal of said voltage interpolation signals, said first voltage interpolation signal having a binary state representing a sub-quantization level one half of said least significant bit quantization level.
14. The flash analog-to-digital converter of claim 13, wherein said time interpolating encoding further comprises:
generate a delayed first comparison signal, having a delay relative to said first comparison signal based on said feedback control signal,
detecting the difference between the second delay time and an occurrence of the delayed first comparison signal, and
generating, based on said detected difference, a third voltage interpolation signal of said voltage interpolation signals, said third voltage interpolation signal representing a third and a fourth of said sub-bins.
15. The flash analog-to-digital converting method of claim 11, wherein said generating a feedback control signal includes generating 2K\u22121\u22121 lower level feedback control signals, and further comprising:
generating 2K\u22121\u22121 different delays, concurrently, of said first comparison signal, based on said 2K\u22121\u22121 lower level feedback control signals;
generating 2K\u22121\u22121 different delays, concurrently, of said second comparison signal, based on said 2K\u22121\u22121 lower level feedback control signals; and
generating 2K\u22121\u22121 voltage interpolation signals, said generating based on detecting a difference between the first delay time and the second delay time,
detecting a difference between the first delay time and a respective occurrence of each of said 2K\u22121\u22121 different delays of said second comparison signal and detecting a difference between the second delay time and a respective occurrence of each of said 2K\u22121\u22121 different delays of said first comparison signal,
wherein said first comparison signal, said second comparison signal, and said 2K\u22121 voltage interpolation signals represent 2K bins within said least significant bit quantization level.