What is claimed is:
1. A voltage generator for providing a bias voltage to a word line, comprising:
a constant current source for producing different levels of current in response to different conditions;
at least one transistor connected in series with said constant current source;
an amplifier responsive to a voltage across two terminals of said transistor; and
a drive circuit responsive to said amplifier for biasing a word line.
2. The voltage generator of claim 1 wherein said constant current source is responsive to different temperature conditions.
3. The voltage generator of claim 1 additionally comprising a laser trimmable device connected with said constant current source.
4. The voltage generator of claim 1 additionally comprising a plurality of fuses connected with said constant current source.
5. The voltage generator of claim 1 additionally comprising a plurality of antifuses connected with said constant current source.
6. A temperature dependent voltage generator, comprising:
a temperature dependent constant current source for producing different levels of current in response to different temperatures;
at least one transistor connected in series with said constant current source;
an amplifier responsive to a voltage across certain terminals of said transistor; and
a drive circuit responsive to said amplifier for providing a voltage.
7. The voltage generator of claim 6 wherein said amplifier is responsive to a voltage across a gate terminal and a source terminal.
8. The voltage generator of claim 6 additionally comprising means connected with said constant current source for controlling the voltage post fabrication.
9. A temperature compensated bias generator for use with an array of load-less four transistor memory cells interconnected by bit lines and word lines, said bias generator comprising:
a temperature dependent constant current source;
a plurality of transistors connected in parallel with one another and in series with said constant current source;
an amplifier responsive to an average voltage across two terminals of said plurality of transistors; and
a drive circuit responsive to said amplifier for providing a bias voltage.
10. The bias generator of claim 9 wherein said average voltage across two terminals includes the average voltage across a gate terminal and a source terminal of each transistor in said plurality of transistors.
11. A bias generator, comprising:
a temperature dependent constant current source,
a constant current source,
a circuit for producing a bias voltage in response to one of said current sources; and
a switch for connecting one of said constant current sources to said circuit.
12. The bias generator of claim 11 wherein said switch is responsive to a test mode signal.
13. The bias generator of claim 11 additionally comprising a laser trimmable device connected to said temperature dependent constant current source.
14. The bias generator of claim 11 additionally comprising a plurality of fuses connected to said temperature dependent constant current source.
15. The bias generator of claim 11 additionally comprising a plurality of antifuses connected to said temperature dependent constant current source.
16. The bias generator of claim 11 additionally comprising a laser trimmable device connected to said constant current source.
17. The bias generator of claim 11 additionally comprising a plurality of fuses connected to said constant current source.
18. The bias generator of claim 11 additionally comprising a plurality of antifuses connected to said constant current source.
19. A combination comprising:
an array of memory cells each comprised of not more than four transistors;
a plurality of digit lines and word lines interconnecting said array of memory cells; and
a bias generator for producing different levels of current in response to different conditions, said bias generator for providing a bias voltage to one of said word lines and digit lines.
20. The combination of claim 19 wherein said bias generator is responsive to temperature.
21. The combination of claim 19 wherein said bias generator is responsive to different test modes.
22. A combination comprising:
an array of memory cells each comprised of not more than four transistors;
a plurality of digit lines and word lines interconnecting said array of memory cells;
a bias generator for providing a temperature sensitive bias voltage to one of said word lines and digit lines in response to a control signal;
a voltage source for providing a fixed bias voltage to one of said word lines and digit lines; and
a switch responsive to the control signal for connecting said voltage source to one of said word lines and digit lines when the control signal disconnects said bias generator.
23. A combination comprising:
an array of memory cells each comprised of not more than four transistors;
a plurality of digit lines and word lines interconnecting said array of memory cells;
a bias generator for providing a temperature sensitive bias voltage to one of said word lines and digit lines;
an inputoutput pad; and
a switch responsive to the control signal for selectively connecting said pad to one of said word lines and digit lines in response to a control signal.
24. A static random access memory, comprising:
an array of memory cells each comprised of not more than four transistors;
a plurality of digit lines and word lines interconnecting said array of memory cells;
a bias generator for producing different levels of current in response to different conditions, said bias generator for providing a bias voltage to one of said word lines and digit lines; and
a plurality of peripheral devices, responsive to said digit lines and said word lines for controlling the input of information to, and output of information from, said array of memory cells.
25. The memory of claim 24 wherein said bias generator is responsive to temperature.
26. The memory of claim 24 wherein said bias generator is responsive to different test modes.
27. A system, comprising:
a microprocessor;
a plurality of memory devices in communication with said microprocessor, each of said memory devices comprising:
an array of memory cells each comprised of not more than four transistors;
a plurality of digit lines and word lines interconnecting said array of memory cells;
a bias generator for producing different levels of current in response to different conditions, said bias generator for providing a bias voltage to one of said word lines and digit lines; and
a plurality of peripheral devices, responsive to said digit lines and said word lines for controlling the input of information to, and output of information from, said array of memory cells.
28. A method of controlling the load current in a load less four transistor memory cell, comprising:
providing a temperature dependent bias voltage to one of the word line and the digit line.
29. The method of claim 28 wherein said step of providing a bias voltage includes the steps of:
generating a temperature dependent constant current;
generating a voltage drop across two terminals of a transistor representative of the access transistors in the memory cell with said temperature dependent constant current; and
sensing said voltage drop to produce the bias voltage.
30. The method of claim 29 additional comprising the steps of generating a plurality of voltage drops across two terminals of a plurality of transistors representative of the access transistors in the memory cell with said temperature dependent constant current, and averaging said voltage drops before said sensing step.
31. A method of controlling the conduction of the access transistors of a load-less, four transistor memory cell, comprising:
applying a temperature dependent bias voltage to control terminals of the access transistors.
32. The method of claim 31 additionally comprising the steps of:
generating a temperature dependent constant current;
generating a voltage drop across two terminals of a transistor representative of the access transistors with said temperature dependent constant current; and
sensing said voltage drop to produce the temperature dependent bias voltage.
33. The method of claim 32 additionally comprising the steps of generating a plurality of voltage drops across two terminals of a plurality of transistors representative of the access transistors in the memory cell with said temperature dependent constant current, and averaging said voltage drops before said amplifying step.
34. A method of modifying the level of current conducted by the access transistors of a load-less, four transistor memory cell when said transistors are in an off-state, comprising:
generating a temperature dependent bias voltage;
providing a test mode bias voltage; and
connecting one of said temperature dependent bias voltage and test mode bias voltage to control terminals of the access transistors.
35. The method of claim 34 wherein said step of generating a temperature dependent bias voltage includes the steps of:
generating a temperature dependent constant current; and
sensing a voltage drop across two terminals of a transistor representative of the access transistors as a result of the application of said temperature dependent constant current to generate the temperature dependent bias voltage.
36. The method of claim 35 additionally comprising the steps of generating a plurality of voltage drops across two terminals of a plurality of transistors representative of the transistors in the memory cell with said temperature dependent constant current, and averaging said voltage drops.
37. A method of regulating a voltage difference between the word line and digit line of a load-less four transistor memory cell, comprising:
applying one of a temperature dependent bias voltage and a test mode bias voltage to one of the word line and digit line.
38. The method of claim 37 additionally comprising the step of generating said test mode bias voltage.
39. The method of claim 37 wherein said test mode bias voltage is applied from an inputoutput pad.
40. The method of claim 37 additionally comprising the steps of:
generating a temperature dependent constant current;
generating a voltage drop across two terminals of a transistor representative of the transistors in the memory cell with said temperature dependent constant current; and
sensing said voltage drop to produce the temperature dependent bias voltage.
41. The method of claim 40 additionally comprising the steps of generating a plurality of voltage drops across two terminals of a plurality of transistors representative of the transistors in the memory cell with said temperature dependent constant current, and averaging said voltage drops before said amplifying step.
42. A method, comprising:
generating a temperature dependent constant current;
generating a fixed constant current;
selecting one of said temperature dependent and fixed constant currents;
generating a plurality of voltage drops representative of the voltage drops across the gate and source terminals of access transistors in a loadless, four transistor cell using said selected constant current;
averaging said voltage drops to produce an average voltage; and
applying said average voltage to the gate terminals of the access transistors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fixing sleeve for a spark plug comprising coolant passages which are arranged in the wall of the fixing sleeve and which are oriented substantially in the longitudinal direction of the spark plug, characterised in that the fixing sleeve comprises a metallic material whose thermal conductivity is over 60 Wm C.
2. The fixing sleeve according to claim 1, characterised in that the fixing sleeve comprises a metallic material whose thermal conductivity is over 80 Wm C.
3. The fixing sleeve according to claim 1 characterised in that the fixing sleeve comprises brass or a brass alloy.
4. The fixing sleeve according to claim 1 characterised in that the fixing sleeve comprises nickel or a nickel alloy.
5. The fixing sleeve according to claim 1 characterised in that mounted to the fixing sleeve is an antechamber which comprises a nickel-chromium alloy with over 25% chromium.
6. The fixing sleeve according to claim 5 wherein said nickel-chromium alloy comprises about 30% chromium.
7. The fixing sleeve according to claim 5 characterised in that the antechamber is surrounded by an annular passage into which the coolant passages open.
8. The fixing sleeve according to claim 1 characterised in that the coolant passages are brought closer to the spark plug in the front region of the fixing sleeve, which region has a screwthread for screwing in the spark plug.
9. The fixing sleeve according to claim 8 characterised in that in the front region of the fixing sleeve the coolant passages have enlargements facing towards the spark plug.
10. The fixing sleeve according to claim 8 characterised in that the configuration of the coolant passages is adapted to the contour of the spark plug in the front region of the fixing sleeve.
11. The fixing sleeve according to claim 8 characterised in that the remaining wall thickness in the front region of the fixing sleeve between the spark plug and coolant passages is partially below 5 mm.
12. The fixing sleeve according to claim 1 characterised in that a plurality of coolant passages is arranged around the spark plug.
13. A cylinder head characterised in that at least one fixing sleeve according to claim 1 is arranged therein.