1. A system for deterring bird strikes incorporated in an aircraft, the system comprising:
at least one light configured to project light at optical wavelengths within an avian species optical sensitivity but having low or no observability by pilots; and
at least one audio projection device configured to broadcast alert or predatory calls within avian species auditory capability,
wherein the audio projection device is capable of audio projection in airflow having speeds up to about 250 KIAS.
2. The system of claim 1, wherein the at least one light is further configured to flash.
3. The system of claim 2, wherein the at least one light is configured to flash at 0.75 Hz.
4. The system of claim 1, wherein the at least one light is configured to project light in a violet range at 380 to 430 nm.
5. The system of claim 1, wherein the at least one light is a first light, the system further comprising:
a second light configured to project light at optical wavelengths within an avian species optical sensitivity but having low or no observability by pilots and being further configured to flash,
wherein the first light and second light are positioned on opposite sides of a fuselage of the aircraft.
6. The system of claim 1, wherein the audio projection device is configured to broadcast at frequencies between about 500 Hz to about 4000 Hz.
7. The system of claim 6, wherein the audio projection device is configured to broadcast at a frequency of about 1500 Hz.
8. The system of claim 1, wherein the audio projection device is mounted inside a forward baggage compartment.
9. The system of claim 1, wherein the audio projection device is mounted on an articulating arm attached to a fuselage of the aircraft, the articulating arm configured to move from a first position integral with the aircraft to a second deployed position directing an output of the audio projection device in a direction forward of the aircraft.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data processing element, comprising:
an input unit configured to provide instructions for scalar, vector and array processing;
a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity;
a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity; and
an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity.
2. The data processing element as recited in claim 1 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector quantity.
3. The data processing element as recited in claim 2 wherein a one-dimensional vector quantity can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.
4. The data processing element as recited in claim 2 wherein a one-dimensional vector quantity can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.
5. The data processing element as recited in claim 1 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector quantity.
6. The data processing element as recited in claim 5 wherein the parallel multiplying accumulator provides a resultant one-dimensional vector quantity.
7. The data processing element as recited in claim 6 wherein the resultant one-dimensional vector quantity is processed in the vector pipeline datapath.
8. A method of operating a data processing element, comprising:
fetching instructions for scalar, vector and array processing;
processing a scalar quantity through a scalar pipeline datapath;
also processing a one-dimensional vector quantity through a vector pipeline datapath employing a vector register; and
further processing a two-dimensional vector quantity through an array pipeline datapath employing a parallel processing structure.
9. The method as recited in claim 8 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector quantity.
10. The method as recited in claim 9 wherein a one-dimensional vector quantity can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.
11. The method as recited in claim 9 wherein a one-dimensional vector quantity can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.
12. The method as recited in claim 8 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector quantity.
13. The method as recited in claim 12 wherein the parallel multiplying accumulator provides a resultant one-dimensional vector quantity.
14. The method as recited in claim 13 wherein the resultant one-dimensional vector quantity is processed in the vector pipeline datapath.
15. a MIMO receiver, comprising:
a MIMO input element, coupled to multiple receive antennas, that provides receive data for scalar, vector and array processing;
a data processing element, including:
an input unit that provides instructions for the scalar, vector and array processing,
a scalar processing unit that provides a scalar pipeline datapath for processing scalar data,
a vector processing unit, coupled to the scalar processing unit, that provides a vector pipeline datapath employing a vector register for processing one-dimensional vector data, and
an array processing unit, coupled to the vector processing unit, that provides an array pipeline datapath having a parallel processing structure for processing two-dimensional vector data; and
a MIMO output element, coupled to the data processing element, that provides an output data stream corresponding to the receive data.
16. The receiver as recited in claim 15 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector data.
17. The receiver as recited in claim 16 wherein one-dimensional vector data can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.
18. The receiver as recited in claim 16 wherein one-dimensional vector data can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.
19. The receiver as recited in claim 15 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector data.
20. The receiver as recited in claim 19 wherein the parallel multiplying accumulator provides resultant one-dimensional vector data.