1. A voltage level translator, comprising:
a pair of cross coupled p-type transistors;
a pair of n-type transistors connectable between complementary inputs and a gate of the one of the p-type transistors; and
a pair of boosting circuits, the gate of the n-type transistors connected to one of the boosting circuits to boost the gate voltage of the n-type transistor, each boosting circuit comprising:
a first drain to source connected transistor gate connected to the gate of its respective n-type transistor; and
a second, diode connected, transistor connected between the gate of its respective n-type transistor and a supply voltage.
2. The voltage level translator of claim 1, and further comprising:
a precharge element to precharge the gate of each of the pair of n-type transistors.
3. The voltage level translator of claim 2, wherein each precharge element comprises:
a thin oxide n-type transistor gate to drain connected between a supply voltage and the gate of one of the first or the second n-type transistors.
4. A voltage level translator, comprising:
a pair of cross coupled p-type transistors;
a pair of n-type transistors connectable between complementary inputs and a gate of the one of the p-type transistors;
a pair of boosting circuits each to boost a gate voltage of the gate of its respective n-type transistor, each boosting circuit comprising:
a first drain to source connected transistor gate connected to the gate of its respective n-type transistor; and
a second, diode connected, transistor connected between the gate of its respective n-type transistor and a supply voltage; and
a precharge element to precharge the gate of each of the pair of n-type transistors.
5. A voltage level translator, comprising:
a first and a second p-type transistor;
a first and a second n-type transistor, the first n-type transistor connected between an input signal and a gate of the second p-type transistor, and the second n-type transistor connected between an input signal and the gate of the first p-type transistor; and
a pair of boosting circuits, the gate of one of the n-type transistors connected to one of the boosting circuits to boost the gate voltage of the n-type transistor, each boosting circuit comprising:
a first drain to source connected transistor gate connected to the gate of its respective n-type transistor; and
a second, diode connected, transistor connected between the gate of its respective n-type transistor and a supply voltage.
6. The voltage level translator of claim 5, and further comprising:
a precharge element to precharge the gate of each of the pair of n-type transistors.
7. The voltage level translator of claim 6, wherein each precharge element comprises:
a thin oxide n-type transistor gate to drain connected between a supply voltage and the gate of one of the first or the second n-type transistors.
8. A voltage level translator, comprising:
a pair of cross coupled p-type transistors;
a pair of n-type transistors connected between complementary inputs and a gate of the one of the p-type transistors;
a pair of boosting circuits, the gate of the n-type transistors connected to one of the boosting circuits to boost the gate voltage of the n-type transistor, each boosting circuit comprising:
a first drain to source connected transistor gate connected to the gate of its respective n-type transistor; and
a second, diode connected, transistor connected between the gate of its respective n-type transistor and a supply voltage; and
a precharge element to precharge the precharge the gate of each of the pair of n-type transistors.
9. The voltage level translator of claim 8, wherein each precharge element comprises:
a thin oxide n-type transistor gate to drain connected between a supply voltage and the gate of one of the first or the second n-type transistors.
10. A memory device comprising:
an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections;
inputoutput circuitry coupled to read and latch a row of data from the memory array; and
a voltage level translator circuit connected to at least one of the control circuitry, the address circuitry, or the inputoutput circuitry, the voltage level translator comprising:
a pair of cross coupled p-type transistors;
a pair of n-type transistors connected between complementary inputs and a gate of the one of the p-type transistors; and
a pair of boosting circuits, the gate of the n-type transistors connected to one of the boosting circuits to boost the gate voltage of the n-type transistor, each boosting circuit comprising:
a first drain to source connected transistor gate connected to the gate of its respective n-type transistor; and
a second, diode connected, transistor connected between the gate of its respective n-type transistor and a supply voltage.
11. A processing system, comprising:
a processor; and
a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
an array of memory cells;
control circuitry to read, write and erase the memory cells;
address circuitry to latch address signals provided on address input connections;
inputoutput circuitry coupled to read and latch a row of data from the memory array; and
a voltage level translator circuit connected to at least one of the control circuitry, the address circuitry, or the inputoutput circuitry, the voltage level translator comprising:
a pair of cross coupled p-type transistors;
a pair of n-type transistors connected between complementary inputs and a gate of the one of the p-type transistors; and
a pair of boosting circuits, the gate of the n-type transistors connected to one of the boosting circuits to boost the gate voltage of the n-type transistor, each boosting circuit comprising:
a first drain to source connected transistor gate connected to the gate of its respective n-type transistor; and
a second, diode connected, transistor connected between the gate of its respective n-type transistor and a supply voltage.
12. A method of boosting gate to source voltage of an n-type transistor in a voltage level translator, comprising:
boosting a gate to source voltage of each of a pair of pull down n-type transistors in the translator, wherein boosting comprises boosting with a drain to source connected transistor having its gate coupled to the gate of its respective n-type transistor and a diode connected transistor connected between the gate of its respective n-type transistor and a supply voltage.
13. The method of claim 12, and further comprising:
clamping a clamping transistor to which the boosting capacitance is also connected.
14. The method of claim 13, wherein clamping comprises:
limiting a voltage at the gate of each n-type transistor to approximately the supply voltage plus a threshold voltage of the clamping transistor.
15. The method of claim 12, and further comprising:
precharging a node connected to the gate of each of the pull down n-type transistors.
16. The method of claim 15, and further comprising:
limiting the voltages at the nodes between the boosting capacitance and the precharge elements.
17. The method of claim 16, wherein limiting is performed with a clamping circuit.
18. The method of claim 12, and further comprising:
precharging the gate of each of the pair of pull down n-type transistors.
19. A method of translating voltage level, comprising:
boosting a gate voltage of the gate of each of a pair of n-type transistors in a level translator; and
precharging the gate of each of the pair of n-type transistors;
wherein boosting comprises boosting with a drain to source connected transistor having its gate coupled to the gate of its respective n-type transistor and a diode connected transistor connected between the gate of its respective n-type transistor and a supply voltage.
20. The method of claim 19, and further comprising:
clamping a clamping transistor, a single clamping transistor connected to each of the n-type transistor gates.
21. The method of claim 20, wherein clamping comprises:
limiting a voltage at the gate of each n-type transistor to approximately the supply voltage plus a threshold voltage of the clamping transistor.
22. The method of claim 19, and further comprising:
limiting the voltages at the nodes between the boosting capacitance and the precharge elements.
23. The method of claim 22, wherein limiting is performed with a clamping circuit.
24. The method of claim 19, wherein precharging comprises:
providing a precharge voltage to the gate of each of the n-type transistors through a gate to source connected thin oxide transistor, the precharge voltage being approximately the supply voltage minus a threshold voltage of the thin oxide transistor.
25. The method of claim 19, and further comprising:
blocking early latching of the level translator.
26. The method of claim 25, wherein blocking comprises:
providing a precharge voltage to the gate of each of the n-type transistors through a gate to source connected thin oxide transistor, the precharge voltage being approximately the supply voltage minus a threshold voltage of the thin oxide transistor.
27. A method of increasing an operating range of supply voltage in a voltage level translator, comprising:
boosting a gate to source voltage of each of a pair of pull down n-type transistors in the translator; and
precharging the gate of each of the pair of n-type transistors;
wherein boosting comprises boosting with a drain to source connected transistor having its gate coupled to the gate of its respective n-type transistor and a diode connected transistor connected between the gate of its respective n-type transistor and a supply voltage.
28. The method of claim 27, and further comprising:
clamping a clamping transistor, a single clamping transistor connected to each of the n-type transistor gates.
29. The method of claim 28, wherein clamping comprises:
limiting a voltage at the gate of each n-type transistor to approximately the supply voltage plus a threshold voltage of the clamping transistor.
30. The method of claim 27, and further comprising:
limiting the voltages at the nodes between the boosting capacitance and the precharge elements.
31. The method of claim 30, wherein limiting is performed with a clamping circuit.
32. The method of claim 27, wherein precharging comprises:
providing a precharge voltage to the gate of each of the n-type transistors through a gate to source connected thin oxide transistor, the precharge voltage being approximately the supply voltage minus a threshold voltage of the thin oxide transistor.
33. The method of claim 27, and further comprising:
blocking early latching of the level translator.
34. The method of claim 33, wherein blocking comprises:
providing a precharge voltage to the gate of each of the n-type transistors through a gate to source connected thin oxide transistor, the precharge voltage being approximately the supply voltage minus a threshold voltage of the thin oxide transistor.
35. A method of expanding an operating voltage range of a level translator circuit, comprising:
boosting a gate voltage of the gate of each of a pair of n-type transistors; and
precharging the gate of each of the pair of n-type transistors, wherein boosting comprises boosting with a drain to source connected transistor having its gate coupled to the gate of its respective n-type transistor and a diode connected transistor connected between the gate of its respective n-type transistor and a supply voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-20. (canceled)
21. A sole for an article of footwear, the sole comprising:
a first area including a first deformation element comprising a foamed material; and
a second area including a second deformation element comprising an open-walled structure free from foamed materials, wherein the second deformation element further comprises at least two side walls and at least one element interconnecting center regions of the side walls.
22. The sole of claim 21, wherein the at least one element interconnecting the center regions of the side walls is placed in tension upon compressive loading of the sole.
23. The sole of claim 21, wherein each side wall comprises a single integral piece.
24. The sole of claim 22, wherein the side walls and the interconnecting element comprise a single piece.
25. The sole of claim 24, wherein the single piece comprises a thermoplastic material.
26. The sole of claim 25, wherein the thermoplastic material has a hardness between about 70 Shore A and about 85 Shore A.
27. The sole of claim 25, wherein the thermoplastic material has a hardness between about 75 Shore A and about 80 Shore A.
28. The sole of claim 21, wherein a thickness of at least one of the interconnecting element and the side walls increases along a length of the second deformation element.
29. The sole of claim 21, wherein the side walls are further interconnected by at least one of an upper side and a lower side.
30. The sole of claim 21 further comprising two second deformation elements arranged adjacent each other.
31. The sole of claim 30, wherein at least one of an upper side and a lower side interconnects adjacent side walls of the two second deformation elements.
32. The sole of claim 31, wherein the two second deformation elements are further interconnected by at least one of an upper connecting surface and a lower connecting surface.
33. The sole of claim 21, wherein the first area is arranged in an aft portion of a heel region of the sole.
34. The sole of claim 21, wherein the second area is arranged in a front portion of a heel region of the sole.
35. The sole of claim 21, wherein the first area is arranged to correspond to metatarsal heads of a wearer’s foot.
36. The sole of claim 35, wherein the second area is arranged fore of the metatarsal heads of the wearer’s foot.
37. The sole of claim 35, wherein the second area is arranged aft of the metatarsal heads of the wearer’s foot.
38. The sole of claim 21, wherein the first deformation element and the second deformation element are arranged below at least a portion of at least one load distribution plate of the sole.
39. The sole of claim 38, wherein the load distribution plate at least partially three-dimensionally encompasses at least one of the first deformation element and the second deformation element.
40. An article of footwear comprising an upper and a sole, the sole comprising:
a first area including a first deformation element comprising a foamed material; and
a second area including a second deformation element comprising an open-walled structure free from foamed materials, wherein the second deformation element further comprises at least two side walls and at least one element interconnecting center regions of the side walls.