What is claimed is:
1. A circuit for phase detection, comprising:
a phase detector including a first input for receiving a first input signal having a first phase angle, and a second input for receiving a second input signal having a second phase angle, said phase detector having first and second outputs;
first and second current sources, the first current source including a reference current input;
first and second reference current sources;
a first switch coupled to the reference current input of the first current source and also coupled to the first and second reference current sources, said first switch for coupling the reference current input of the first current source to one of the first and second reference current sources, the first switch having a control input connected to the first output of the phase detector;
a second switch coupled to the second current source for connecting and disconnecting the second current source to and from a predetermined node, the second switch having a control input connected to the second output of the phase detector; and
a signal output coupled to the first and second current sources for providing an output current based on a phase deviation between the first and second phase angles.
2. The circuit of claim 1, including a supply potential terminal and a reference potential terminal, the first and second current sources arranged in series configuration between the supply potential terminal and the reference potential terminal.
3. The circuit of claim 2, wherein the predetermined node is the signal output.
4. The circuit of claim 2, including a third reference current source, the second current source having a reference current input, and the second switch coupled between the third reference current source and the reference current input of the second current source for connecting and disconnecting the third reference current source and the reference current input of the second current source.
5. The circuit of claim 1, wherein the predetermined node is the signal output.
6. The circuit of claim 1, including a third reference current source, the second current source having a reference current input, and the second switch coupled between the third reference current source and the reference current input of the second current source for connecting and disconnecting the third reference current source and the reference current input of the second current source.
7. A phase locked loop circuit, comprising:
a phase detector including a first input for receiving a first input signal having a first phase angle, and a second input for receiving a second input signal having a second phase angle, said phase detector having first and second outputs;
first and second current sources, the first current source including a reference current input;
first and second reference current sources;
a first switch coupled to the reference current input of the first current source and also coupled to the first and second reference current sources, said first switch for coupling the reference current input of the first current source to one of the first and second reference current sources, the first switch having a control input connected to the first output of the phase detector;
a second switch coupled to the second current source for connecting and disconnecting the second current source to and from a predetermined node, the second switch having a control input connected to the second output of the phase detector;
a signal output coupled to the first and second current sources for providing an output current based on a phase deviation between the first and second phase angles;
a controlled oscillator having a control input and an output;
a loop filter connected between the signal output and the control input of the controlled oscillator;
a frequency divider coupled between the output of the controlled oscillator and the first input of the phase detector; and
a reference frequency generator coupled to the second input of the phase detector.
8. The circuit of claim 7, including a supply potential terminal and a reference potential terminal, the first and second current sources arranged in series configuration between the supply potential terminal and the reference potential terminal.
9. The circuit of claim 8, wherein the predetermined node is the signal output.
10. The circuit of claim 9, wherein the frequency divider includes a fractional-N divider having a control input for receiving a conditioned modulation signal.
11. The circuit of claim 8, wherein the frequency divider includes a fractional-N divider having a control input for receiving a conditioned modulation signal.
12. The circuit of claim 8, including a third reference current source, the second current source having a reference current input, and the second switch coupled between the third reference current source and the reference current input of the second current source for connecting and disconnecting the third reference current source and the reference current input of the second current source.
13. The circuit of claim 12, wherein the frequency divider includes a fractional-N divider having a control input for receiving a conditioned modulation signal.
14. The circuit of claim 7, wherein the frequency divider includes a fractional-N divider having a control input for receiving a conditioned modulation signal.
15. The circuit of claim 7, wherein the predetermined node is the signal output.
16. The circuit of claim 15, wherein the frequency divider includes a fractional-N divider having a control input for receiving a conditioned modulation signal.
17. The circuit of claim 7, including a third reference current source, the second current source having a reference current input, and the second switch coupled between the third reference current source and the reference current input of the second current source for connecting and disconnecting the third reference current source and the reference current input of the second current source.
18. The circuit of claim 17, wherein the frequency divider includes a fractional-N divider having a control input for receiving a conditioned modulation signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A reed for a saxophone, comprising:
one to six concave grooves which are formed from a file mark to a heel portion in a longitudinal direction of a reed body in a straight line,
wherein a depth of each of the one to six concave grooves extends from a surface of a curved surface downward to a plane extending between top points of vertical side surfaces of a reed body.
2. The reed for a saxophone according to claim 1, wherein said one to six concave groves is formed in a longitudinal direction of the reed body in a straight line, and if one concave groove is formed, it is formed at a center equally dividing a width of the reed body, and if two are formed, each of the concave grooves is formed at a center of each of three parts formed by equally dividing the width of the reed body, and if three concave grooves are formed, each of the concave grooves is formed at a center of each of four parts, and if four concave grooves are formed, each of the concave grooves is formed at a center of each of five parts obtained by equally dividing the width of the same.