1. A memory circuit, comprising:
a sector including a memory location having a memory cell and a complementary memory cell; and
a sense amplifier circuit configured to:
determine a value stored in the memory location during a first read mode, and
determine a first state of the memory cell and a second state of the complementary memory cell during a second read mode.
2. The memory circuit of claim 1, wherein:
the memory cell includes a non-volatile memory cell; and
the complementary memory cell includes a complementary non-volatile memory cell.
3. The memory circuit of claim 1, wherein the sense amplifier is configured to determine the value stored in the memory location in response to a first state of the memory cell and a second state of the complementary memory cell.
4. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the value stored in the memory location in response to a difference between a first state of the memory cell and a second state of the complementary memory cell.
5. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the value stored in the memory location in response to a difference between a first voltage stored by the memory cell and a second voltage stored by the complementary memory cell.
6. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the first state of the memory cell and the second state of the complementary memory cell by reading the memory cell independently of the complementary memory cell.
7. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the first state of the memory cell and the second state of the complementary memory cell by reading the complementary memory cell independently of the memory cell.
8. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, the other memory cells, and the other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine a state of the sector in response to the number.
9. The memory circuit of claim 8, wherein the particular state includes an erased state.
10. The memory circuit of claim 8, wherein the particular state includes a programmed state.
11. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, the other memory cells, and the other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine that the state of the sector includes the particular state if the number of states is below a threshold.
12. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, the other memory cells, and the other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine that the state of the sector includes a state opposite to the particular state if the number of states is above a threshold.
13. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine that the state of the sector includes a written state if the number of states is between two thresholds.
14. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, to determine a state of the sector in response to the number, and, if the determined state of the sector is not an erased state, then to erase the memory cell, complementary memory cell, other memory cells and other complementary memory cells, and to program the memory cell, complementary memory cell, other memory cells and other complementary memory cells.
15. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, to determine a state of the sector in response to the number, and, if the determined state of the sector is not an erased state, then to erase the memory cell, complementary memory cell, other memory cells and other complementary memory cells, to program the memory cell, complementary memory cell, other memory cells and other complementary memory cells, and to write data to at least one of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells.
16. A memory circuit, comprising:
a plurality of sectors of memory cells,
wherein each memory cell is configured to take a programmed state or an erased state,
the memory cells each including a direct memory cell and a complementary memory cell,
a read circuit configured to select at least one of the sectors, determine a number of memory cells in the selected sector that are in the programmed state, determine a number of memory cells in the selected sector that are in the erased state, and identify a condition of the selected sector according to a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
17. The memory circuit of claim 16, wherein said identified condition is one of:
a non-written condition when the memory cells are in equal states; and
a written condition wherein the memory cells are in different states.
18. The memory circuit of claim 16, wherein the read circuit includes a comparison circuit configured to compare electrical quantities associated with a least part of the memory cells in the selected sector to a threshold value.
19. The memory circuit of claim 17, wherein the read circuit identifies the selected sector as not in the non-written condition when the number of memory cells of the selected sector in a given state exceeds a limit value.
20. The memory circuit of claim 19, wherein the read circuit includes a counting circuit configured to count the memory cells of the selected sector in the given state and wherein counting is stopped when the number of memory cells of the selected sector in the given state exceeds the limit value.
21. The memory circuit of claim 17, wherein the read circuit identifies the selected sector as in the written condition when a predetermined subset of locations in the selected sector stores a predetermined sequence of logic values.
22. The memory circuit of claim 16, further comprising:
a select circuit configured to select one of the sectors in response to a received command; and
a control circuit configured, if the selected sector is identified as in the written condition, to bring all the memory cells of the selected sector into the programmed state and then bring all the memory cells of the selected sector from the programmed state to the erased state.
23. The memory of claim 16, further comprising:
a select circuit configured to select one of the sectors in response to a writing instruction of a word in the selected sector, the word comprising a target logic value of each location of the selected sector; and
a control circuit configured, if the selected sector is identified as in the written condition, to bring all the memory cells of the selected sector into the programmed state, and then bring all the memory cells of the selected sector from the programmed state to the erased state, and then bring each direct memory cell of the selected sector into the state corresponding to the respective target logic value, and bring each complementary memory cell of the selected sector into the state corresponding to the complement of the respective target logic value.
24. The memory of claim 16, further comprising:
a select circuit configured to select one of the sectors; and
a control circuit configured, if the selected sector is identified as in the non-written condition with the memory cells in the programmed state, to bring all the memory cells of the selected sector into the erased state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An audio andor video generation apparatus which is arranged in operation to generate audio andor video signals, said audio andor video generation apparatus, comprising
a recording means which is arranged in operation to record said audio andor video signals on a recording medium,
a meta data generation processor which is arranged in operation to generate meta data identifying the content of said audiovideo signals in response to said audiovideo signals, and
a communications processor which is operable to communicate said meta data separately from said recording medium.
2. An audio andor generation apparatus as claimed in claim 1, wherein said meta data generation processor is operable to receive a pre-defined list of takes of audiovideo signals to be generated, said meta data generation processor being arranged in operation to generate said meta data in association with said list of takes, and said communications processor is arranged to communicate said meta data in assocation with said list of takes.
3. An audio andor generation apparatus as claimed in claim 1 or 2, wherein said meta data generated by said meta data generation processor is at least one picture which is representative of an image from said recorded video signals.
4. An audio andor generation apparatus as claimed in claim 3, wherein said meta data processor is arranged in operation to associate said picture with an address on said recording medium at which said image is recorded, said address forming part of said meta data communicated by said communications processor.
5. An audio andor video generation apparatus as claimed in claim 4, wherein said meta data are the in and out points of a take of the audiovideo signals.
6. An audio andor video generation apparatus as claimed in any of claims 1 to 5, wherein said meta data includes a unique identification code for identifying the audiovideo signals.
7. An audio andor video generation apparatus as claimed in claim 6, wherein the unique identification code includes a UMID or the like.
8. A receiving apparatus for receiving and displaying the meta data communicated by the audio andor video generation apparatus claimed in any of claims 1 to 7.
9. A meta data generation apparatus comprising
a meta data generation processor which is arranged in operation to receive audio andor video signals, and to generate meta data identifying the content of said audiovideo signals in response to said audiovideo signals, and
a communications processor which arranged to communicate said meta data separately from said recording medium.
10. A meta data generation apparatus as claimed in claim 9, comprising
a data store, wherein said meta data generation processor is arranged to receive a pre-defined list of takes of audio andor video signals to be generated and stored in said data store, said meta data generation processor being arranged in operation to generate said meta data in association with said list of takes, and said communications processor is operable to communicate said meta data in assocation with said list of takes.
11. A meta data generation apparatus as claimed in claim 9 or 10, wherein said meta data generated by said meta data generation processor includes at least one picture which is representative of an image from said recorded video signals.
12. A meta data generation apparatus as claimed in claim 11, wherein said picture is arranged in operation to be associated with an address on said recording medium at which said image is recorded, said address forming part of said meta data communicated by said communications processor.
13. A method of generating audio andor video signals representative of an audio andor visual source, said method comprising the steps of
recording said audio andor video signals on a recording medium,
generating meta data identifying the content of said audiovideo signals in response to said audiovideo signals, and
communicating said meta data separately from said recording medium.
14. A storage medium on which information signals are recorded, said information signals being representative of the meta data generated by the generation apparatus according to any of claims 1 to 7 and claims 9 to 12.
15. A signal representing the meta data communicated by the generation apparatus according to any of claims 1 to 7 and 9 to 12.
16. A video generation apparatus which is arranged in operation to generate video signals representative of an image source, said video generation apparatus comprising
a recording processor which is arranged in operation to record said video signals on a recording medium, and
a meta data generation processor which is arranged in operation to receive said video signals and to generate at least one sample image which is representative of a video image from said recorded video signals, and to associate said sample image with an address on said recording medium at which said video image is recorded.
17. An video generation apparatus as claimed in claim 16, wherein said at least one sample image is first and second sample images, said first of said sample images being generated for a video image at an in point of said at least part of said video signals and said second of said sample images being generated for a video image at an out point of said at least part of said video signals, and said address is a first and second address, said first address indicating the place on said recording medium at which said in point video image is recorded, and said second address indicating the place on said recording medium at which said out point video image is recorded.
18. A video generation apparatus as claimed in any of claim 16 or 17, comprising
an activity detector coupled to said meta data generation processor and arranged in operation to receive said video signals and to generate an activity signal indicative of a relative change of content of said video signals, wherein
said meta data generation processor is arranged in operation to generate a plurality sample images, each of which is representative of a video image from said recorded video signals, said sample images being generated at times of change of content of said video signals indicated by said activity signal, an address of each of said sample images providing the location on said recording medium at which the corresponding video image is recorded.
19. A video generation apparatus as claimed in claim 18, wherein said activity detector generates said activity signal by forming a histogram of colour components of said video image and determining a rate of change of said colour components.
20. A video generation apparatus as claimed in claim 18 or 19, wherein said activity detector generates said activity signal by from motion vectors of image components of said video image signal.
21. A video generation apparatus as claimed in any of claims 18 to 20,
a display processor which is arranged in operation to provide a visible representation of said sample images.
22. A video generation apparatus as claimed in any of claims 16 to 21, wherein said video signals are representative of a plurality of video material items, and said meta data generation processor is arranged in operation to generate a preference marker in response to commands from a user in association with selected ones of said video material items.
23. A video generation apparatus as claimed in claim 22, wherein said meta data generation processor is arranged in operation to record data representative of said preference marker on said recording medium.
24. A video generation apparatus as claimed in any of claims 16 to 23, comprising
a data store coupled to said meta data generation processor, said at least one sample image and said address being stored in said data store separately from said recording medium.
25. A video generation apparatus as claimed in claim 24, wherein said data representing said preference marker is stored in said data store in association with the sample image and the address corresponding to a selected video material item.
26. A video generation apparatus as claimed in any of claims 16 to 25, wherein said recording medium is a random access memory, and said address indicates a place in said memory where said video image is recorded.
27. A video generation apparatus as claimed in any of claims 16 to 26, wherein said recording medium is a linear recording medium and said address is a time code corresponding to a place on said recording medium where said video image is recorded.
28. A video generation apparatus as claimed in any of claims 16 to 27, wherein said meta data processor generates said sample images in accordance with a compression encoding process such as the Joint Photographic Experts Group compression encoding process.
29. A video generation apparatus as claimed in any of claims 16 to 28, wherein said meta data includes a unique identification code for identifying the video signals.
30. A video generation apparatus as claimed in claim 29, wherein the unique identification code is a UMID or the like.
31. A meta data generation processor comprising
a sample image generation processor which is arranged in operation to receive video signals being recorded on to a recording medium, and to generate at least one sample image which is representative of a video image from the video signals being recorded, and
an address detector which is arranged in operation to associate the sample image with an address on the recording medium at which the video image is recorded.
32. A meta data generation processor as claimed in claim 31, wherein said at least one sample image is first and second sample images, said first of said sample images being generated for a video image at an in point of said at least part of said video signals and said second of said sample images being generated for a video image at an out point of said at least part of said video signals, and said address is a first and second address, said first address indicating the place on said recording medium at which said in point video image is recorded, and said second address indicating the place on said recording medium at which said out point video image is recorded.
33. A meta data generation processor as claimed in claim 31 or 32, comprising
an activity detector arranged in operation to receive said video signals and to generate an activity signal indicative of a relative change of content of said video signals, wherein
said sample image generation processor is arranged in operation to generate a plurality sample images, each of which is representative of a video image from said recorded video signals, said sample images being generated at times of change of content of said video signals indicated by said activity signal, an address of each of said sample images providing the location on said recording medium at which the corresponding video image is recorded.
34. A meta data generation processor as claimed in claim 33, wherein said activity detector generates said activity signal by forming a histogram of colour components of said video image and determining a rate of change of said colour components.
35. A meta data generation processor as claimed in claim 33 or 34, wherein said activity detector generates said activity signal by from motion vectors of image components of said video image signal.
36. A meta data generation processor as claimed in any of claims 31 to 35, comprising
a sample image generation processor which is arranged in operation to receive video signals and to generate at least one sample image which is representative of a video image from the video signals, and
an address detector which is arranged in operation to associate the sample image with an address of the video image in the video signals.
37. A method of generating video signals representative of an image source, said method comprising the steps of
forming said video signals,
recording said video signals on a recording medium,
generating at least one sample image which is representative of a video image from said recorded video signals, and
associating said sample image with an address on said recording medium at which said video image is recorded.
38. A method of generating video signals as claimed in claim 37, wherein the step of generating at least one sample image comprises the step of
generating first and second sample images, said first of said sample images being generated for a video image at an in point of said at least part of said video signals and said second of said sample images being generated for a video image at an out point of said at least part of said video signals, and the step of associating said at least one sample image with an address comprises the step of
generating a first and second address, said first address indicating the place on said recording medium at which said in point video image is recorded, and said second address indicating the place on said recording medium at which said out point video image is recorded.
39. A method of generating video signals as claimed in claim 38, wherein the step of generating at least one sample image comprises the step of
generating an activity signal indicative of a relative change of content of said video signals, and
generating a plurality sample images, each of which is representative of a video image from said recorded video signals, said sample images being generated at times of change of content of said video signals indicated by said activity signal, and the step of associating said at least one sample image with an address comprises the step of
providing the location of each of said plurality of sample images on said recording medium at which the corresponding video image is recorded.
40. A recording medium on which is stored data representative of the sample image and the address of the video signals representative of the sample image on the recording medium generated by the video generation apparatus according to any of claims 16 to 30, or the meta data generation processor according to any of claims 31 to 36.
41. A signal representing the sample image and the address of the video signals corresponding to said sample image which are generated by the video generation apparatus according to any of claims 16 to 30, or the meta data generation processor according to any of claims 31 to 36.
42. A system for generating an audio andor video production comprising
an acquisition processor operable in use to receive instructions from a user which instructions are representative of a list content items for the audio andor video production,
an audio andor video generation apparatus arranged in operation to receive information representative of list of said content items, and operable in use to generate audio andor video signals in accordance with said content items of said list, and
an ingestion processor which is arranged in operation to receive said list of content items, and said audio andor video signals and to form said audio andor video production by associating said audio andor video signals with said list of content items.
43. A system as claimed in claim 42, wherein said audio andor video signals are representative of a plurality of takes captured by said generation apparatus in association with said content items, and said ingestion processor is arranged to form said audio andor video production by selecting for at least one content item at least one of a plurality of takes associated with said at least one content item.
44. A system as claimed in claim 42 or 43, wherein said audio andor video generation apparatus is provided with a meta data generation tool which is arranged in operation to generate meta data describing said audio andor video signals in combination with said content item list.
45. A system as claimed in claims 42, 43 or 44, wherein said meta data generator generation tool is arranged to indicate a preferred one of said plurality of takes to be used for said at least one content item, and said ingestion processor is arranged to select said preferred take for said at least one content item consequent upon said indication.
46. A system as claimed in claim 45, wherein said indication is a good shot marker or the like.
47. An acquisition processor for use in generating an audiovideo production, comprising
a control processor coupled to a data store,
a user interface coupled to the control processor for receiving commands from a user, and
a communications interface coupled to the control processor and arranged in operation to receive data representative of pre-planned audiovideo material items, wherein said control processor is arranged in use to communicate data indicative of at least one of said pre-planned audiovideo material items to be generated by an audiovideo generation apparatus.
48. An acquisition processor as claimed in claim 47, wherein said pre-planned audiovideo material items are representative of a plurality of takes of audiovideo material items to be acquired by said audiovideo generation apparatus.
49. An acquisition processor as claimed in claim 47 or 48, wherein said communications interface is arranged to receive signals representative of meta data identifying at least one audiovideo material item recorded onto a recording medium corresponding to said at least one of said pre-planned audiovideo material items.
50. An acquisition processor as claimed in claim 49, wherein said control processor operates to store said meta data identifying said at least one recorded audiovideo material item in said data store in association with the corresponding pre-planned audiovideo material item.
51. An acquisition processor as claimed in any of claims 47 to 50, wherein said user interface is arranged to receive a command indicative of a preferred one of a plurality of audiovideo material items to be used for one of said pre-planned audiovideo material items, and said control processor is arranged in operation to store said indication in said data store in association with said selected audiovideo material item.
52. An acquisition processor as claimed in claim 51, wherein said indication is a good shot marker or the like.
53. An audio andor video generation apparatus for generating audio andor video signals, said audio andor video generation apparatus comprising
a recording means which is arranged in operation to record said audio andor video signals on a recording medium,
a communications interface arranged in operation to receive data indicative of at least one of a plurality of pre-planned audiovideo material items, and
a meta data generation processor coupled to said communications interface and to said recording means and arranged in operation to generate meta data identifying at least one audiovideo material item recorded on to said recording medium corresponding to said at least one pre-planned audiovideo material item.
54. An audio andor video generation apparatus as claimed in claim 53, wherein said meta data generation processor is arranged to operate in combination with said communications interface to communicate said meta data to an acquisition processor.
55. An audio andor video generation apparatus as claimed in any of claim 53 or 54, comprising
a user interface coupled to said meta data generation processor and arranged in use to receive a command indicative of a preferred one of a plurality of audiovideo material items to be used for one of said pre-planned audiovideo material items, and said meta data generation processor is arranged in operation include in said meta data identifying said preferred one of said audiovideo material items data representing said preferred indication.
56. An audio andor video generation apparatus as claimed in claim 55, wherein said preferred indication includes a good shot marker or the like.
57. A computer program providing computer executable instructions, which when loaded on to a data processor configures said data processor to operate as an audio andor video generation apparatus as claimed in claims 1 to 7, or a meta data generation apparatus as claimed in any of claims 9 to 12, or a video generation apparatus as claimed in claims 16 to 30, or a meta data generation processor as claimed in claims 31 to 36, or a system for generating an audio andor video production as claimed in claims 42 to 46, or acquisition processor as claimed in any of claims 47 to 52, or an audio andor video generation apparatus as claimed in any of claims 53 to 56.
58. A computer program having computer executable instructions, which when loaded on to a data processor causes the processor to operate in accordance with the method according to any of claims 13, 37 to 39.
59. A computer program product having a computer readable medium having recorded thereon information signals representative of the computer program claimed in any of claims 57 or 58.
60. A system for generating an audio andor video production as herein before described with reference to the accompanying drawings.
61. An acquisition processor as herein before described with reference to the accompanying drawings.
62. An audio andor video generation apparatus as herein before described with reference to the accompanying drawings.
63. A method of generating audio andor video signals as herein before described with reference to the accompanying drawings.
64. A video generation apparatus as herein before described with reference to the accompanying drawings.
65. A method of recording video signals as herein before described with reference to the accompanying drawings.