1.-20. (canceled)
21. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:
a semiconductor substrate having a first area and a second area, wherein the first area is substantially surrounded by the second area and is isolated from the second area by a field oxide region;
a pixel array formed in the first area of the semiconductor substrate, wherein the pixel array includes a plurality of MOSFET transistors each having a gate with a gate insulating layer; and
a logic circuit formed in the second area of the semiconductor substrate, wherein the logic circuit includes a plurality of MOSFET transistors each having a gate with a gate insulating layer;
wherein the gate insulating layer of each MOSFET transistor in the pixel array is thicker than the gate insulating layer of each MOSFET transistor in the logic circuit.
22. The CMOS image sensor of claim 21, wherein each MOSFET transistor in the pixel array includes, as its gate insulating layer, a double layer of insulating material, and wherein each MOSFET transistor in the logic circuit includes, as its gate insulating layer, a single layer of insulating material.
23. The CMOS image sensor of claim 22, wherein the single layer of insulating material has a thickness ranging from about 10 \u212b to about 40 \u212b, and wherein the double layer of insulating material has a thickness ranging from about 40 \u212b to about 90 \u212b.
24. The CMOS image sensor of claim 21, wherein the semiconductor substrate includes a p-type epitaxial layer having doped regions configured to form the plurality of MOSFET transistors in the pixel array, and wherein the gate insulating layers of the plurality of MOSFET transistors in the pixel array include a layer of thermally-oxidized silicon oxide (SiO2) formed over the p-type epitaxial layer.
25. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:
a semiconductor substrate including a first area and a second area, wherein the first and second areas are isolated from one another by an isolation region;
pixel sensors formed by MOSFET transistors in the first area and arranged in a pixel array, wherein each of the MOSFET transistors in the first area has a gate with a gate insulating layer of a first thickness; and
a logic circuit formed by MOSFET transistors in the second area, wherein the MOSFET transistors in the second area have gates with gate insulating layers of a second thickness;
wherein the first thickness is greater than the second thickness.
26. The CMOS image sensor of claim 25, wherein each MOSFET transistor forming the pixel sensors in the pixel array includes, as its gate insulating layer, a double layer of insulating material having the first thickness, and wherein some of the MOSFET transistors forming the logic circuit include, as their gate insulating layer, a single layer of insulating material having the second thickness.
27. The CMOS image sensor of claim 26, wherein the single layer of insulating material has a thickness ranging from about 10 \u212b to about 40 \u212b, and wherein the double layer of insulating material has a thickness ranging from about 40 \u212b to about 90 \u212b.
28. The CMOS image sensor of claim 25, wherein each MOSFET transistor in the pixel array includes, as its gate insulating layer, a double layer of insulating material, and wherein each MOSFET transistor in the logic circuit includes, as its gate insulating layer, a single layer of insulating material.
29. The CMOS image sensor of claim 25, wherein the first thickness has a range from about 10 \u212b to about 40 \u212b, and wherein the second thickness has a range from about 40 \u212b to about 90 \u212b.
30. The CMOS image sensor of claim 25, wherein the isolation region comprises a field oxide surrounding the first area.
31. The CMOS image sensor of claim 25, wherein some of the MOSFET transistors in the logic circuit are configured to interact with some of the MOSFET transistors in the pixel array.
32. A method of making a complementary metal-oxide semiconductor (CMOS) image sensor, the method comprising:
doping regions in a substrate to form MOSFET transistors in first and second areas of the substrate, wherein the MOSFET transistors in the first area are used to form pixel sensors of a pixel array, and wherein the MOSFET transistors in the second area are used to form a logic circuit;
forming a field oxide in a region around the first area to isolate the MOSFET transistors in the first area from the MOSFET transistors in the second area;
depositing a first insulating layer concurrently over both the first and second areas of the substrate;
removing the first insulating layer from the second area while leaving the first insulating layer over the first area intact;
depositing a second insulating layer concurrently over both the first and second areas of the substrate;
removing the second insulating layer from selected regions of the second area to form gates of the MOSFET transistors in the logic circuit; and
removing both the first and second gate insulating layers from selected areas of the first area to form gates of the MOSFET transistors of the pixel sensors, wherein the gate of each MOSFET transistor in the first area has a thickness corresponding to a combined thickness of the first and second insulating layers, and wherein the gate of each MOSFET transistor in the second area has a thickness that is less than a combined thickness of the first and second insulating layers.
33. The method of claim 32, wherein said removing the first insulating layer from the second area while leaving the first insulating layer over the first area intact comprises:
applying a mask over the first insulating layer, wherein the mask includes an opening exposing the first insulating layer in the first area; and
using a removal process to remove the exposed first insulating layer in the second area.
34. The method of claim 33, wherein said using a removal process is carried out through a wet-etching process.
35. The method of claim 33, wherein said using a removal process is carried out through a hydrofluoric acid (HF) process.
36. The method of claim 33, wherein said using a removal process is carried out through a buffered oxide etchant (BOE) process.
37. The method of claim 33, wherein said using a removal process is carried out through an 02 plasma process.
38. A method of making a complementary metal-oxide semiconductor (CMOS) image sensor, the method comprising:
growing an epitaxial layer on a surface of a substrate;
doping a first area of the substrate for forming MOSFET transistors of a plurality of pixel sensors in a pixel array;
doping a second area of the substrate for forming MOSFET transistors of a logic circuit;
depositing a field oxide in the epitaxial layer in a region around the first area to isolate the pixel array from the logic circuit;
depositing a first insulator layer over the first and second areas during a first deposition process;
removing the first insulator layer from the second area of the substrate;
depositing a second insulator layer over the first and second areas during a second deposition process;
patterning the first and second insulator layers in the first area to form gates of the MOSFET transistors in the pixel array; and
patterning the second insulator layer in the second area to form gates of the MOSFET transistors of the logic circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for monitoring transaction execution on the Internet, comprising the steps of:
acquiring monitoring data of a transaction executing on the Internet, and abstracting abnormal data from the monitoring data;
acquiring an abnormal service based on the abnormal data; and
locating a source of execution failure in architecture layers based on the abnormal service.
2. The method for monitoring transaction execution on the Internet of claim 1, wherein the step of locating the source of execution failure in the architecture layers based on the abnormal service comprises:
detecting whether there is an abnormality in an architecture layer in which the abnormal service exists, if so, then recording an abnormal point in the architecture layer in which the abnormal service exists;
starting from a next architecture layer associated with the abnormal service and detecting layer by layer in sequence from a front end to a back end, and determining whether the detected architecture, layer exists any abnormality, if so, then recording an abnormal point in the detected architecture layer;
processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure.
3. The method for monitoring transaction execution on the Internet of claim 2, wherein the step of locating the source of execution failure in the architecture layers based on the abnormal service further comprises:
determining whether there is a next architecture layer associated with the abnormal service at the architecture layer where the abnormal service occurs, if so, then performing the step of starting from the next architecture layer associated with the abnormal service and detecting in sequence from the front end to the back end layer by layer;
or else, locating the recorded abnormal point as the source of execution failure.
4. The method for monitoring transaction execution on the Internet of claim 2, wherein the step of processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure comprises:
abstracting an abnormal point corresponding to a maximum priority as the source of execution failure from the recorded abnormal points based on priorities corresponding to the architecture layers.
5. The method for monitoring transaction execution on the Internet of claim 2, wherein the step of processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure comprises:
abstracting an abnormal point corresponding to an architecture layer at a rearmost end from the recorded abnormal points;
locating the abstracted abnormal point as the source of execution failure.
6. The method for monitoring transaction execution on the Internet of claim 5, wherein, after the step of processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure of the transaction, the method further comprises:
presenting the source of execution failure and the abnormal point in a failure locating page.
7. A system for monitoring transaction execution on the Internet, comprising:
a data monitoring module configured for acquiring monitoring data of a transaction on the Internet, and abstracting abnormal data from the monitoring data;
an abnormal service acquiring module configured for acquiring an abnormal service based on the abnormal data; and
a detecting module configured for locating a source of execution failure o in architecture layers based on the abnormal service.
8. The system for monitoring transaction execution on the Internet of claim 7, wherein the detecting module comprises:
an initial detecting unit configured for detecting whether there is an abnormality in an architecture layer in which the abnormal service exists, if so, then recording an abnormal point in the architecture layer in which the abnormal service exists;
a layer by layer detecting unit configured for starting from a next architecture layer associated with the abnormal service and detecting layer by layer in sequence from a front end to a back end, and determining whether there exists any abnormality on the detected architecture layer, if so, then recording an abnormal point in the detected architecture layer;
a processing unit configured for processing the recorded abnormal points in accordance with a sequence of the architecture layers in the architecture hierarchy to locate the source of execution failure.
9. The system for monitoring transaction execution on the Internet of claim 8, wherein the processing module further comprises:
a layer determining unit configured for determining whether there is a next architecture layer associated with the abnormal service at the architecture layer where the abnormal service occurs, if so, then informing the layer by layer detecting unit, or else, informing the processing unit; wherein
the processing unit is further configured for locating the abnormal point recorded as the source of execution failure.
10. The system for monitoring transaction execution on the Internet of claim 8, wherein the processing unit is further configured for abstracting an abnormal point corresponding to a maximum priority as the source of execution failure from the recorded abnormal points based on priorities corresponding to the architecture layers.
11. The system for monitoring transaction execution on the Internet of claim 8, wherein the processing unit is further configured for abstracting an abnormal point corresponding to an architecture layer at a rearmost end from the recorded abnormal points, and locating the abstracted abnormal point as the source of execution failure.
12. The system for monitoring transaction execution on the Internet of claim 11, wherein the system also presents the source of execution failure and the abnormal point in a failure locating page.
13. A computer readable storage medium for storing computer executable instructions, wherein the computer executable instructions are configured for controlling the method of monitoring the transactions on the Internet, wherein the method comprising:
acquiring monitoring data of a transaction on the Internet, and abstracting abnormal data from the monitoring data;
acquiring an abnormal service based on the abnormal data; and
locating a source of execution failure in architecture layers based on the abnormal service.
14. The computer readable storage medium of claim 13, wherein the step of locating the source of execution failure in the architecture layers based on the abnormal service comprises:
detecting whether there is an abnormality in an architecture layer in which the abnormal service exists, if so, then recording an abnormal point in the architecture layer in which the abnormal service exists;
starting from a next architecture layer associated with the abnormal service and detecting layer by layer in sequence from a front end to a back end, and determining whether the detected architecture layer exists any abnormality, if so, then recording an abnormal point in the detected architecture layer;
processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure.
15. The computer readable storage medium of claim 14, wherein the step of locating the source of execution failure in the architecture layers based on the abnormal service further comprises:
determining whether there is a next architecture layer associated with the abnormal service at the architecture layer where the abnormal service occurs, if so, then performing the step of starting from the next architecture layer associated with the abnormal service and detecting in sequence from the front end to the back end layer by layer;
or else, locating the recorded abnormal point as the source of execution failure.
16. The computer readable storage medium of claim 14, wherein the step of processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure further comprises:
abstracting an abnormal point corresponding to a maximum priority as the source of execution failure from the recorded abnormal points based on priorities corresponding to the architecture layers.
17. The computer readable storage medium of claim 14, wherein the step of processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure comprises:
abstracting an abnormal point corresponding to an architecture layer at a rearmost end from the recorded abnormal points;
locating the abstracted abnormal point as the source of execution failure.
18. The computer readable storage medium of claim 17, wherein after the step of processing the recorded abnormal points in sequence from the front end to the back end in the architecture hierarchy to locate the source of execution failure of the transaction, the computer executable instructions are further operable for:
presenting the source of execution failure and the abnormal point in a failure locating page.