1. A communication control apparatus comprising:
at least one processor coupled via a bus to a memory, the processor being programmed to control one or more of:
an acquiring unit configured to acquire moving image data to be transmitted to a receiving apparatus and delay time information according to playback time of the moving image data;
a generating unit configured to generate packets using the moving image data acquired by the acquiring unit, wherein the generated packets are stored in a memory;
a determining unit configured to determine, in accordance with the delay time information acquired by the acquiring unit, a transmission interval of the packets generated using the moving image data of a plurality of frame including an intra-coded frame and an inter-coded frame such that the transmission interval of the packets of the plurality of frames is longer than a transmission interval based on a number of packets of the intra-coded frame and a frame rate of the moving image data; and
a transmission unit configured to transmit the packets generated by the generating unit to the receiving apparatus based on the transmission interval determined by the determining unit.
2. The communication control apparatus according to claim 1, wherein the determining unit determines an upper limit value of the transmission interval of the packets based on at least one of data characteristic information and communication characteristic information and determines the transmission interval of the packets based on the determined upper limit value.
3. The communication control apparatus according to claim 2, wherein the communication characteristic information includes an accuracy level of a clock of the communication control apparatus, and the determining unit determines packets to be successively transmitted at transmission timing points based on the accuracy level of the clock.
4. The communication control apparatus according to claim 2, wherein the moving image data represents stream data, and the data characteristic information includes at least one of a time needed for decoding or playing back the entire stream data, the size of the entire stream data, and the size of the stream data for each of predetermined processing times.
5. The communication control apparatus according to claim 4, wherein the predetermined processing time is a time based on the inverse of the frame rate.
6. The communication control apparatus according to claim 2, wherein the moving image data represents stream data, and the data characteristic information includes at least one of a time needed for decoding or playing back a predetermined unit of processing that constitutes the stream data and that includes at least one frame, the size of stream data for each of the predetermined units of processing, the largest frame size in the predetermined unit of processing, and one of a decoding time and playing back time of a frame included in the predetermined unit of processing.
7. The communication control apparatus according to claim 2, wherein the communication characteristic information includes at least one of the size of the packet, an accuracy level of a clock referenced when transmission processing of the packet is performed, a communication rate available for communication, a buffer size needed for decoding or playing back stream data, and an error rate of an error occurring in a communication path.
8. The communication control apparatus according to claim 1,
wherein the acquiring unit acquires a bit rate of the moving image data corresponding to a first time period and a second time period following the first time period, and
the determining unit determines the transmission interval of the packets based on the bit rate of the moving image data such that the transmission intervals of the moving image data of the first and second time periods are equal when the bit rate of the moving image data of the first time period is lower than a predetermined bit rate and the bit rate of the moving image data of the second time period is higher than the predetermined bit rate.
9. A method for controlling communication, the method comprising:
acquiring moving image data to be transmitted to a receiving apparatus and delay time information according to playback time of the moving image data;
generating packets using the moving image data acquired in the acquiring step;
determining, in accordance with the delay time information acquired in the acquiring step, a transmission interval of the packets generated using the moving image data of a plurality of frames including an intra-coded frame and an inter-coded frame such that the transmission interval of the packets of the plurality of frames is longer than a transmission interval based on a number of packets of the intra-coded frame and a frame rate of the moving image data; and
transmitting packets generated in the generating step based on the transmission interval determined in the determining step.
10. The method according to claim 9, wherein an upper limit value of the transmission interval of the packets is determined in the determining step based on at least one of data characteristic information and communication characteristic information, and the transmission interval of the packets is determined based on the upper limit value.
11. The method according to claim 9, wherein a bit rate of the moving image data corresponding to a first time period and a second time period following the first time period is acquired in the acquiring step, and the transmission interval of the packets is determined in the determining step based on the bit rate of the moving image data such that the transmission intervals of the moving image data of the first and second time periods are equal when the bit rate of the moving image data of the first time period is lower than a predetermined bit rate and the bit rate of the moving image data of the second time period is higher than the predetermined bit rate.
12. A computer-executable program code stored on a non-transitory storage medium for causing a computer to execute a method for controlling communication, the method comprising:
acquiring moving image data to be transmitted to a receiving apparatus and delay time information according to playback time of the moving image data;
generating packets using the moving image data acquired in the acquiring step;
determining, in accordance with the delay time information acquired in the acquiring step, a transmission interval of the packets generated using the moving image data of a plurality of frames including an intra-coded frame and an inter-coded frame such that the transmission interval of the packets of the plurality of frames is longer than a transmission interval based on a number of packets of the intra-coded frame and a frame rate of the moving image data; and
transmitting the packets generated in the generating step based on the transmission interval determined in the determining step.
13. The computer-executable program code according to claim 12, wherein an upper limit value of the transmission interval of the packets is determined in the determining step based on at least one of data characteristic information and communication characteristic information, and the transmission interval of the packets is determined based on the upper limit value.
14. The computer-executable program code according to claim 12, wherein a bit rate of the moving image data corresponding to a first time period and a second time period following the first time period is acquired in the acquiring step, and
the transmission interval of the packets is determined in the determining step based on the bit rate of the moving image data such that the transmission intervals of the moving image data of the first and second time periods are equal when the bit rate of the moving image data of the first time period is lower than a predetermined bit rate and the bit rate of the moving image data of the second time period is higher than the predetermined bit rate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for forming a Lateral Double-Diffused MOSFET (LDMOS), comprising:
providing a semiconductor substrate having a first conductivity type;
forming a first shallow trench isolation (STI) structure in the semiconductor substrate;
applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure, wherein the second conductivity type is opposite to the first conductivity type;
applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region, wherein a depth of the counter-doped region is less than a depth of the drift region;
forming a body region on one side of the drift region in the semiconductor substrate, wherein the body region has the first conductivity type; and
forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.
2. The method according to claim 1, further including a second ion implantation before the counter-doping ion implantation, wherein:
dopants of the second conductivity are doped into the semiconductor substrate to form a first doped region in the semiconductor substrate such that the first doped region includes connected first portion and second portion, wherein the first portion is located in the drift region, the second region is located in the semiconductor substrate outside the drift region, and a depth of the first doping region is less than the depth of the drift region.
3. The method according to claim 2, wherein the depth of the counter-doped region is less than a depth of the first doped region.
4. The method according to claim 3, wherein a tilt angle of the second ion implantation is about 15\xb0 to about 45\xb0, an ion implantation energy is about 150 KeV to about 250 KeV, and an ion dose is about 1E12 atomcm2 to about 1.5E13 atomcm2.
5. The method according to claim 3, wherein a tilt angle of the counter-doping ion implantation is about 0\xb0 to about 7\xb0, an ion implantation energy is about 30 KeV to about 100 KeV, and an ion dose is about 1E12 atomcm2 to about 1.5E13 atomcm2.
6. The method according to claim 3, wherein the first ion implantation further includes a first-step ion implantation and a second-step ion implantation, wherein:
a tilt angle of the first-step ion implantation is about 0\xb0 to about 7\xb0, an ion implantation energy is about 500 KeV to about 1M KeV, and an ion dose is about 5E11 atomcm2 to about 1E13 atomcm2; and
a tilt angle of the second-step ion implantation is about 0\xb0 to about 7\xb0, an ion implantation energy is about 250 KeV to about 500 KeV, and an ion dose is about 5E11 atomcm2 to about 1E13 atomcm2.
7. The method according to claim 2, wherein a formation process of the drift region includes:
forming a mask layer having an opening to expose a portion of the semiconductor substrate; and
applying the mask layer as a mask for the first ion implantation to dope dopants of the second conductivity type into the semiconductor substrate to form the drift region to surround the first STI structure.
8. The method according to claim 7, wherein formation processes of the first doped region and the counter-doped region include:
applying the mask layer as the mask for the second ion implantation to dope dopants of the second conductivity into the semiconductor substrate to form the first doped region, wherein the first doped region includes connected first portion and second portion, the first portion is located in the drift region, the second region is located in the semiconductor substrate outside the drift region, and the depth of the first doping region is less than the depth of the drift region;
applying the mask layer as the mask for the counter-doping ion implantation to dope dopants of the first conductivity type into the drift region to form the counter-doping region having a depth less than the depth of the drift region.
9. The method according to claim 1, wherein the LDMOS is an N-type LDMOS, the dopants of the first conductivity type are P-type dopants, and the dopants of the second conductivity type are N-type dopants.
10. The method according to claim 1, wherein the LDMOS is a P-type LDMOS, the dopants of the first conductivity type are N-type dopants, and the dopants of the second conductivity type are P-type dopants.
11. The method according to claim 9, wherein the P-type dopants are one or more of boron ions, indium ions, and gallium ions, and the N-type dopants are one or more of phosphorus ions, arsenic ions, and antimony ions.
12. The method according to claim 1, further including:
forming a drain region in the drift region on one side of the first STI structure facing away from the gate structure and doped with dopants of the second conductivity type; and
forming a source region in the body region on one side of the gate region and doped with dopants of the second conductivity type.
13. The method according to claim 12, wherein a depth of the drain region is greater than the depth of the counter-doped region.
14. The method according to claim 1, wherein the gate structure includes a gate dielectric on the semiconductor substrate, a gate electrode on the gate dielectric, and sidewalls on both sides of the gate electrode and the gate dielectric.
15. An LDMOS (Lateral-Double-Diffused MOSFET), comprising:
a semiconductor substrate having a first conductivity type;
a first shallow trench isolation (STI) structure in the semiconductor substrate;
a drift region having a second conductivity type, in the semiconductor substrate and surrounding the first STI structure, wherein the second conductivity type is opposite to the first conductivity type;
a counter-doped region having the first conductivity type and in the drift region, wherein a depth of the counter-doped region is less than a depth of the drift region;
a body region having the first conductivity type and on one side of the drift region in the semiconductor substrate; and
a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region and another end of the gate structure extends to an area on the first STI structure.
16. The LDMOS according to claim 15, further including a first doped region in the semiconductor substrate having the second conductivity type, wherein:
the first doped region includes connected first portion and second portion, the first portion is located in the drift region, the second portion is located in the semiconductor substrate outside the drift region, and a depth of the first doped region is less than the depth of the drift region but greater than the depth of the counter-doped region.
17. The LDMOS according to claim 16, wherein a doping concentration of the dopants of the first conductivity type is about 1E12 atomcm3 to about 1.5E13 atomcm3 in the counter-doped region; a doping concentration of the dopants of the second conductivity type is about 1E12 atomcm3 to about 1.5E13 atomcm3 in the first doped region; and a doping concentration of the dopants of the second conductivity type is about 5E11 atomcm3 to about 1E13 atomcm3 in the drift region.
18. The LDMOS according to claim 15, wherein the LDMOS is an N-type LDMOS, the dopants of the first conductivity type are P-type dopants, and the dopants of the second conductivity type are N-type dopants.
19. The LDMOS according to claim 15, wherein the LDMOS is a P-type LDMOS, the dopants of the first conductivity type are N-type dopants, and the dopants of the second conductivity type are P-type dopants.
20. The LDMOS according to claim 15, wherein the LDMOS is one of an N-type LDMOS and a P-type LDMOS.