1. A backlight unit comprising:
an arrangement surface on which a plurality of light sources are arranged; and
a plurality of reflection surfaces which are erected from a plurality of edges of the arrangement surface and reflect a light from the plurality of light sources,
wherein the light emitted from the light sources and the light reflected from the plurality of reflection surfaces irradiate to an irradiation area surrounded by the plurality of reflection surfaces;
the plurality of reflection surfaces are each inclined at an inclination angle smaller than 90 degrees with respect to extension surface of the arrangement surface which extends toward the outside of the reflection surface;
at least one reflection surface of the plurality of reflection surfaces includes a large inclination area inclined at a large inclination angle and a small inclination area inclined at a small inclination angle; and
the light source arranged close to the large inclination area is disposed closer to the outside frame of the irradiation area than the other light sources arranged close to the small inclination area in plan view from the irradiation area.
2. A backlight unit comprising:
an arrangement surface on which a plurality of light sources are arranged; and
a plurality of reflection surfaces which are erected from a plurality of edges of the arrangement surface and reflect a light from the plurality of light sources,
wherein the light emitted from the light sources and the light reflected from the plurality of reflection surfaces irradiate to an irradiation area surrounded by the plurality of reflection surfaces;
the plurality of reflection surfaces are each inclined at an inclination angle smaller than 90 degrees with respect to extension surface of the arrangement surface which extends toward the outside of the reflection surface;
at least one reflection surface of the plurality of reflection surfaces includes a large inclination area inclined at a large inclination angle and a small inclination area inclined at a small inclination angle; and
the large inclination area is provided at a position to which a larger amount of light is emitted from the light sources and the small inclination area is provided at a position to which a smaller amount of light is emitted from the light sources.
3. The backlight unit according to claim 1, wherein the reflection surface is formed in a surface which continuously connects the large inclination area and the small inclination area.
4. The backlight unit according to claim 1, further comprising:
a case which includes a bottom plate and a plurality of side walls erected from edges of the bottom plate,
wherein the arrangement surface on which the plurality of light sources are arranged is placed on an inner surface of the bottom plate, and
wherein the plurality of reflection surfaces from which the light emitted from the plurality of light sources is reflected are arranged on inner surfaces of the plurality of side walls.
5. The backlight unit according to claim 1, further comprising:
a case which includes a bottom plate and a plurality of side walls erected from edges of the bottom plate,
wherein the bottom plate is the arrangement surface on which the plurality of light sources are arranged, and
wherein the plurality of reflection surfaces on which the light emitted from the plurality of light sources is reflected are arranged on inner surfaces of the plurality of side walls.
6. The backlight unit according to claim 4, wherein a space is formed between the outside of the small inclination area and the inside of the side wall.
7. The backlight unit according to claim 6, wherein an electronic component is provided in the space.
8. The backlight unit according to claim 1, wherein a direction of the peak of the amount of light emitted from the light sources is inclined at an angle from 50 degrees to 80 degrees with respect to a front direction of the light sources.
9. An electro-optical device comprising:
the backlight unit according to claim 1; and
a display panel which is disposed to overlap with the irradiation area of the backlight unit,
wherein the display panel includes an effective display area for displaying an image, and
wherein in plan view from the irradiation area, an outside frame of the effective display area overlaps with the plurality of reflection area of the backlight unit.
10. The electro-optical device according to claim 9, wherein the effective display area is provided within the irradiation area.
11. An electronic apparatus comprising the electro-optical device according to claim 9.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A decoder architecture comprising:
an input buffer configured to receive a plurality of codewords to be processed, wherein the input buffer is configured to receive each of the plurality of codewords at a pre-determined fixed rate;
a decoder configured to receive a first codeword from the input buffer and process the first codeword, the decoder processing the first codeword only for an amount of time required for the first codeword to become substantially error free, wherein an average decoding speed of the decoder is set such that an average read speed of the decoder from the input buffer is faster than the pre-determined fixed rate of receiving the plurality of codewords in the input buffer; and
logic in communication with each of the decoder and the input buffer, the logic configured to determine when the first codeword processed by the decoder becomes substantially error free, wherein the logic generates a signal for loading a second codeword from the input buffer into the decoder responsive to the logic determining that the first codeword has become substantially error free.
2. The decoder architecture of claim 1, wherein a time difference between the pre-determined fixed rate at which the input buffer receives each of the plurality of codewords and the average read speed of the decoder is accumulated over multiple codewords, the accumulated time difference providing additional time for the decoder to decode a codeword requiring longer than the average decoding speed to become substantially error free.
3. The decoder architecture of claim 1, wherein the pre-determined fixed rate corresponds to a value between a maximum time required for the decoder to process a worst case codeword and a minimum time required to decode each of a majority of the plurality of codewords.
4. The decoder architecture of claim 1, further comprising a counter to limit a maximum amount of time for a given codeword to be processed by the decoder.
5. The decoder architecture of claim 4, further comprising an output buffer configured to receive codewords from the decoder and output each codeword at a rate synchronized to the pre-determined fixed rate.
6. The decoder architecture of claim 1, wherein the decoder is an iterative decoder.
7. The decoder architecture of claim 6, wherein the iterative decoder comprises one of a low density parity check (LDPC) decoder, a Hamming decoder, or a Turbo decoder.
8. The decoder architecture of claim 6, wherein the logic determines that the first codeword processed by the decoder has become substantially error free upon the first codeword passing all parity checks of an H matrix associated with the iterative decoder.
9. The decoder architecture of claim 1 wherein the decoder receives the plurality of codewords at a variable rate from the input buffer.
10. A method for decoding a plurality of codewords, the method comprising:
loading a plurality of codewords to be processed into an input buffer, wherein the loading the plurality of codewords into the input buffer is at a pre-determined fixed rate;
transferring a first codeword from the input buffer to a decoder;
processing the first codeword in the decoder, wherein an average decoding speed of the decoder is set such that an average read speed of the decoder from the input buffer is faster than the pre-determined fixed rate of loading the plurality of codewords into the input buffer;
determining when the first codeword processed by the decoder becomes substantially error free; and
generating a signal for loading a second codeword from the input buffer into the decoder responsive to a determination that the first codeword has become substantially error free.
11. The method of claim 10, wherein a time difference between the pre-determined fixed rate at which the input buffer receives each of the plurality of codewords and the average read speed of the decoder is accumulated over multiple codewords, the accumulated time difference providing additional time for the decoder to decode a codeword that requires longer than the average decoding speed to become substantially error free.
12. The method of claim 10, wherein the pre-determined fixed rate corresponds to a value between a maximum time required for the decoder to process a worst case codeword and a minimum time required to decode each of a majority of the plurality of codewords.
13. The method of claim 12, wherein the maximum time required for the decoder to process a worst case codeword and the minimum time required to decode each of a majority of the plurality of codewords are determined empirically based on application requirements.
14. The method of claim 10, further comprising limiting a maximum amount of time for a given codeword to be processed by the decoder.
15. The method of claim 14, further comprising providing an output buffer in communication with the decoder, the output buffer receiving codewords from the decoder and outputting each codeword at a rate synchronized to the pre-determined fixed rate.
16. The method of claim 10, wherein the decoder is an iterative decoder.
17. The method of claim 16, wherein the iterative decoder comprises one of a low density parity check (LDPC) decoder, a Hamming decoder, or a Turbo decoder.
18. The method of claim 16, wherein determining when the first codeword processed by the decoder becomes substantially error free comprises determining that the first codeword processed by the decoder has become substantially error free upon the first codeword passing all parity checks of an H matrix associated with the iterative decoder.
19. The method of claim 10 wherein the plurality of codewords are transferred from the input buffer to the decoder at a variable rate.