1. A method for erasing a floating-gate transistor, then checking and refreshing the floating-gate transistor when it is in the erased state, comprising:
erasing, checking, and erase refreshing the floating-gate transistor;
a) wherein erasing includes:
applying a negative erase voltage to a control gate of the floating-gate transistor; and
applying a collective positive erase voltage to sources of a group of floating-gate transistors having the floating-gate transistor to be erased; and
b) wherein erase refreshing includes:
applying a negative erase voltage to the control gate of the floating-gate transistor; and
selectively applying a positive erase refresh voltage to a drain of the floating-gate transistor.
2. The method according to claim 1 wherein the positive refresh erase voltage is selectively supplied by a programming latch of the floating-gate transistor.
3. The method according to claim 2 wherein the positive refresh erase voltage is equal to a programming voltage supplied by the latch when the floating-gate transistor is programmed.
4. The method according to claim 1, further comprising checking a threshold voltage of the floating-gate transistor, including reading the transistor with a first read voltage and reading the transistor with a second read voltage.
5. The method of claim 1, further comprising taking the drain of the floating-gate transistor to an electric potential that does not interfere with a tunnel effect mechanism acting between the control gate and a source of the floating-gate transistor, and providing the erasing of the floating-gate transistor.
6. The method of claim 5 wherein taking the drain of the floating-gate transistor to the electric potential includes taking the drain to a high impedance potential.
7. The method of claim 1, further comprising taking the source and a channel of the floating-gate transistor to an electric potential that does not interfere with a tunnel effect mechanism acting between the control gate and the drain of the floating-gate transistor, and providing the refreshing of the erased floating-gate transistor.
8. The method of claim 7 wherein taking the source and the channel of the floating-gate transistor to the electric potential includes taking the source and the channel to null or negative potentials.
9. A method for checking and refreshing a page of Flash memory having a plurality of floating-gate transistors linked by their control gates to a common word line, and linked by their drains to different bit lines, the Flash memory having programming latches linked to the bit lines to selectively apply a programming voltage to the drains of the floating-gate transistors, the method comprising:
erasing a group of floating-gate transistors of the page by;
applying a negative erase voltage to the word line; and
applying a collective positive erase voltage to sources of the group of floating-gate transistors to be erased; and
refreshing the floating-gate transistors of the page that are in the erased state, by:
applying a negative erase voltage to the word line; and
selectively applying a positive erase refresh voltage to the bit lines linked to the drains of floating-gate transistors that are to be refreshed.
10. The method according to claim 9 wherein the positive erase voltage is supplied by programming latches.
11. The method according to claim 10 wherein the positive erase voltage is equal to the programming voltage.
12. The method according to claim 9, further comprising checking a threshold voltage of the floating-gate transistors of the page, including reading the transistors with a first read voltage applied to the word line, and reading the transistors with a second read voltage applied to the word line, a transistor only being refreshed if two bits read in the transistor with the two read voltages, have different values.
13. The method according to claim 9, wherein the checking and the refreshing of a page comprises:
i) reading all the transistors of the page with a first read voltage, by group of M transistors, and loading into a buffer memory groups of M bits read with the first read voltage;
ii) reading a group of M transistors of the page with a second read voltage;
iii) logically combining bit by bit the M bits read with the second read voltage and the M bits read with the first read voltage loaded into the buffer memory;
iv) loading M bits forming the result of the logic combination into the buffer memory;
v) repeating ii), iii) and iv) for each subsequent group of M transistors, until the page has been entirely checked; and
vi) successively loading into programming latches the groups of M bits present in the buffer memory, each loading operation being accompanied by an application of the negative erase voltage to the word line and by activation of the programming latches.
14. The method according to claim 13 wherein logically combining bit-by-bit includes using EXCLUSIVE OR logic gates to perform the logic combination.
15. The method according to claim 9, further comprising supplying an address of the page to be checked using a non-volatile counter having memory cells linked to a special word line of the Flash memory.
16. The method according to claim 15 wherein checking the page includes checking an address of the page that varies according to a column address of a first group of M non-programmed memory cells found in the counter.
17. The method according to claim 9, further comprising checking and refreshing floating-gate transistors in a programmed state.
18. A flash memory comprising:
a memory array having a plurality of floating-gate transistors linked by their control gates to word lines, and by their drains to bit lines, the transistors linked to a same word line forming one page of the memory array;
programming latches linked to the bit lines to selectively apply a programming voltage to the drains of the floating-gate transistors;
a counter for designating an address of at least one page to be checked;
means for checking a threshold voltage of floating-gate transistors in a programmed state of a page designated by the counter, and for reprogramming programmed transistors having a threshold voltage below a first determined threshold;
means for erasing floating gate transistors by applying a collective positive erase voltage to first terminals of the floating gate transistors; and
means for checking a threshold voltage of floating-gate transistors in an erased state of the page designated by the counter, and for refreshing erased transistors having a threshold voltage above a second determined threshold by selectively applying a positive erase refresh voltage to second terminals of the floating gate transistors.
19. The flash memory according to claim 18 wherein the means for refreshing erased transistors are arranged for:
applying a negative erase voltage to the word line to which the erased transistors are linked; and
selectively applying the positive erase refresh voltage to the bit lines linked to the drains of floating-gate transistors that are to be refreshed.
20. The memory according to claim 19 wherein the positive erase voltage is supplied by programming latches.
21. The memory according to claim 20 wherein the positive erase voltage is equal to the programming voltage.
22. The memory according to claim 18 wherein the means for checking the threshold voltage of floating-gate transistors in the erased state comprise:
means for reading the transistors with a first read voltage;
means for reading the transistors with a second read voltage; and
means for comparing data read in the transistors with the two read voltages.
23. The memory according to claim 18 wherein the means for checking the threshold voltage of floating-gate transistors in the erased state comprise a buffer memory and a logic combiner and are arranged for:
i) reading all the transistors of the page with a first read voltage by group of M transistors, and loading into the buffer memory groups of M bits read with the first read voltage;
ii) reading a group of M transistors of the page with a second read voltage;
iii) logically combining bit by bit the M bits read with the second read voltage and the M corresponding bits read with the first read voltage and loaded into the buffer memory;
iv) loading into the buffer memory the M bits forming a result of the logic combinations;
v) repeating ii), iii) and iv) for each subsequent group of M transistors, until the page has been fully checked; and
vi) successively loading into programming latches groups of M bits present in the buffer memory, each loading operation being accompanied by an application of the negative erase voltage to the word line and by an activation of the programming latches.
24. The memory according to claim 23 wherein the logic combiner comprises EXCLUSIVE OR logic gates.
25. The memory according to claim 18 wherein the counter is a non-volatile counter comprising memory cells linked to a special word line of the Flash memory.
26. A memory device having a plurality of floating gate transistors, the memory device comprising:
circuit blocks to erase, check, and erase refresh at least one of the floating-gate transistors;
a) wherein the erase circuit block includes:
first circuitry to apply a negative erase voltage to a control gate of the floating-gate transistor; and
second circuitry to apply a collective positive erase voltage to sources of a group of floating-gate transistors having the floating-gate transistor to be erased; and
b) wherein the erase refresh circuit block includes:
third circuitry to apply a negative erase voltage to the control gate of the floating-gate transistor; and
fourth circuitry to selectively apply a positive erase refresh voltage to a drain of the floating-gate transistor.
27. The memory device of claim 26 wherein the floating gate transistors comprise part of flash memory.
28. The memory device of claim 26, further comprising:
fifth circuitry to take the drain of the floating-gate transistor to an electric potential that does not interfere with a tunnel effect mechanism acting between the control gate and a source of the floating-gate transistor; and
sixth circuitry to take the source and a channel of the floating-gate transistor to an electric potential that does not interfere with a tunnel effect mechanism acting between the control gate and the drain of the floating-gate transistor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A magnetic resonance imaging device comprising at least:
a) a main magnet system for generating a steady magnetic field in a measuring space of the magnetic resonance imaging device;
b) a gradient system for generating a magnetic gradient field in said measuring space; and
c) an eddy current shield system including;
at least one perforated eddy current screen, the at least one perforated eddy current screen being flexibly connected to the main magnet system.
2. The magnetic resonance imaging device according to claim 1, wherein the or each perforated eddy current screen is designed in a way that the degree of perforation is in the range of 0.1% to 95%.
3. The magnetic resonance imaging device according to claim 1, wherein the or each eddy current screen has a thickness being thin enough to minimize radiation of acoustic noise and being thick enough to maximize shielding against the magnetic field radiated by the gradient system.
4. The magnetic resonance imaging device according to claim 1, wherein the or each eddy current screen has a thickness in the range of 0.01 mm to 10 mm.
5. The magnetic resonance imaging device according to claim 4, wherein the or each eddy current screen has a thickness in the range of 1 mm to 5 mm.
6. The magnetic resonance imaging device according to claim 3, wherein the or each eddy current screen has an increased thickness in the region in which the eddy current screen is mounted to the main magnet system.
7. The magnetic resonance imaging device according to claim 1, wherein the or each eddy current screen is flexibly attached to the main magnet system by elastic mounting means, especially by flexible rubber means.
8. A magnetic resonance imaging device comprising at least:
a) a main magnet system for generating a steady magnetic field in a measuring space of the magnetic resonance imaging device;
b) a gradient system for generating a magnetic gradient field in said measuring space; and
c) an eddy current shield system;
wherein the eddy current shield system comprises at least one perforated eddy current screen,
wherein the or each perforated eddy current screen is assigned to the main magnet system,
wherein the or each perforated eddy current screen is designed as a constraining layer structure,
wherein the constraining layer structure comprises at least one perforated plate-like layer and at least one perforated visco-elastic layer.
9. The magnetic resonance imaging device according to claim 8, wherein the or each perforated eddy current screen is designed in a way that the degree of perforation is in the range of 10% to 50%.
10. The magnetic resonance imaging device according to claim 8, wherein the constraining layer structure comprises two perforated plate-like layers and one perforated visco-elastic layer, wherein the visco-elastic layer is sandwiched between the two plate-like layers.
11. A magnetic resonance imaging device comprising:
a) a main magnet system for generating a steady magnetic field in a patient receiving bore of the magnetic resonance imaging device, the magnet system defining annular side faces extending radially outward from the bore;
b) a gradient system for generating a magnetic gradient field in said patient receiving bore; and
c) at least one eddy current screen positioned at least in the region of the two side faces of the main magnet system.
12. The magnetic resonance imaging device according to claim 11, wherein the at least one eddy current screen is positioned in the region of the side faces of the main magnet system and in the region of the bore hole between the main magnet system and the gradient system.
13. A magnetic resonance imaging device comprising at least:
a) a main magnet system for generating a stead magnetic field in a measuring bore of the magnetic resonance imaging device;
b) a gradient system disposed in the bore for generating a magnetic gradient field in said measuring bore; and
c) a perforated eddy current screen positioned at least in the the bore between the main magnet system and the gradient system to shield the main magnet system from acoustic frequency eddy currents.
14. A magnetic resonance imaging device according to claim 13, wherein the eddy current screen is also positioned on lateral flanges of the main magnet system.