What is claimed is:
1. A differential circuit comprising:
a first high side transistor coupled to a first differential output node and having a control node coupled to a bias node;
a second high side transistor coupled to a second differential output node and having a control node coupled to the bias node;
a first booster circuit coupled between the control node of the first high side transistor and the second differential output node;
a second booster circuit coupled between the control node of the second high side transistor and the first differential output node.
2. The circuit of claim 1 wherein the first and second booster circuits are differentiators.
3. The circuit of claim 1 wherein the first booster circuit comprises:
a first capacitor coupled between the control node of the first high side transistor and the second differential output node; and
a first resistor coupled between the control node of the first high side transistor and the bias node.
4. The circuit of claim 3 wherein the second booster circuit comprises:
a second capacitor coupled between the control node of the second high side transistor and the first differential output node; and
a second resistor coupled between the control node of the second high side transistor and the bias node.
5. The circuit of claim 1 further comprising:
a first low side transistor coupled to the first differential output node; and
a second low side transistor coupled to the second differential output node.
6. The circuit of claim 5 further comprising:
a first input transistor coupled to a control node of the first low side transistor and having a control node coupled to a first differential input node; and
a second input transistor coupled to a control node of the second low side transistor and having a control node coupled to a second differential input node.
7. The circuit of claim 1 further comprising:
a third high side transistor coupled between the first high side transistor and the first differential output node and having a control node coupled to a first reference node; and
a fourth high side transistor coupled between the second high side transistor and the second differential output node and having a control node coupled to the first reference node.
8. The circuit of claim 7 further comprising:
a fifth high side transistor coupled between the third high side transistor and the first differential output node and having a control node coupled to a second reference node; and
a sixth high side transistor coupled between the fourth high side transistor and the second differential output node and having a control node coupled to the second reference node.
9. The circuit of claim 5 further comprising:
a third low side transistor coupled between the first low side transistor and the first differential output node and having a control node coupled to a first reference node; and
a fourth low side transistor coupled between the second low side transistor and the second differential output node and having a control node coupled to the first reference node.
10. The circuit of claim 9 further comprising:
a fifth low side transistor coupled between the third low side transistor and the first differential output node and having a control node coupled to a second reference node; and
a sixth low side transistor coupled between the fourth low side transistor and the second differential output node and having a control node coupled to the second reference node.
11. The circuit of claim 1 wherein the first and second high side transistors are PMOS transistors.
12. The circuit of claim 5 wherein the first and second low side transistors are NMOS transistors.
13. An amplifier circuit comprising:
a differential input pair;
a first low side transistor coupled to a first differential output node and having a control node coupled to a first branch of the differential input pair;
a second low side transistor coupled to a second differential output node and having a control node coupled to a second branch of the differential input pair;
a first high side transistor coupled to the first differential output node;
a second high side transistor coupled to the second differential output node;
a first RC circuit having a first node coupled to a control node of the first high side transistor and a second node coupled the second differential output node; and
a second RC circuit having a first node coupled to a control node of the second high side transistor and a second node coupled to the first differential output node.
14. The circuit of claim 13 wherein the first RC circuit comprises:
a first capacitor coupled between the second differential output node and the control node of the first high side transistor; and
a first resistor coupled between the control node of the first high side transistor and a bias node.
15. The circuit of claim 14 wherein the second RC circuit comprises:
a second capacitor coupled between the first differential output node and the control node of the second high side transistor; and
a second resistor coupled between the control node of the second high side transistor and the bias node.
16. The circuit of claim 13 wherein the first and second high side transistors are PMOS.
17. The circuit of claim 13 wherein the first and second low side transistors are NMOS.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus comprising:
at least one processor;
a computer readable memory storing a program of instructions;
wherein the program of instructions is configured to, with the memory and the at least one processor, cause the apparatus to perform actions comprising at least:
exchanging first timing information with a device with which the apparatus communicates over a wireless link, wherein the first timing information is exchanged over a synchronization channel with the device; and wherein the first timing information allows maintaining essentially the same time between the apparatus and the device;
upon receiving a timing-over-packet packet from the device, wherein the timing-over-packet packet originates at a master with second timing information, passing the packet to an egress point of the apparatus;
calculating a residence time of the packet in the wireless link, wherein the residence time represents a difference between a time represented by a timestamp of the packet and a time shown by a clock of the apparatus when the packet reaches the egress point of the apparatus, wherein the timestamp represents an arrival time of the packet at an ingress point of the device and wherein the timestamp of the packet is stored in a correction field of the packet;
updating the timestamp of the packet with the residence time of the packet, wherein updating the timestamp of the packet comprises updating the correction field of the packet;
recalculating a checksum of the packet; and
transmitting the packet out of the egress point of the apparatus to a second device.
2. The apparatus of claim 1, wherein the actions further comprise verifying the checksum of the packet.
3. The apparatus of claim 1, wherein the egress point of the packet is between a media independent interface layer and a physical layer of the apparatus.
4. The apparatus of claim 1, wherein the synchronization channel is a dedicated channel.
5. The apparatus of claim 1, wherein the synchronization channel is a virtual channel in a radio bearer used for the wireless link.
6. A method comprising:
configuring at least one processor to cause an apparatus to perform actions comprising at least:
exchanging first timing information with a device with which the apparatus communicates over a wireless link, wherein the first timing information is exchanged over a synchronization channel with the device; and wherein the first timing information allows maintaining essentially the same time between the apparatus and the device;
upon receiving a timing-over-packet packet from the device, wherein the packet originates at a master with second timing information, passing the packet to an egress point of the apparatus;
calculating a residence time of the packet in the wireless link, wherein the residence time represents a difference between a time represented by a timestamp of the packet and a time shown by a clock of the apparatus when the packet reaches the egress point of the apparatus, wherein the timestamp represents an arrival time of the packet at an ingress point of the device, wherein the timestamp of the packet is stored in a correction field of the packet;
updating the timestamp of the packet with the residence time of the packet, wherein updating the timestamp comprises updating the correction field of the packet;
recalculating a checksum of the packet; and
transmitting the packet out of the egress point of the apparatus to a second device.
7. The method of claim 6, wherein the actions further comprise verifying the checksum of the packet.
8. The method of claim 6, wherein the egress point of the packet is between a media independent interface layer and a physical layer of the apparatus.
9. A non-transitory computer readable medium storing a program of instructions, execution of which by a processor configures an apparatus to perform actions comprising at least:
exchanging first timing information with a device with which the apparatus communicates over a wireless link, wherein the first timing information is exchanged over a synchronization channel with the device; and wherein the first timing information allows maintaining essentially the same time between the apparatus and the device;
upon receiving a timing-over-packet packet from the device, wherein the packet originates at a master with second timing information, passing the packet to an egress point of the apparatus;
calculating a residence time of the packet in the wireless link, wherein the residence time represents a difference between a time represented by a timestamp of the packet and a time shown by a clock of the apparatus when the packet reaches the egress point of the apparatus, wherein the timestamp represents an arrival time of the packet at an ingress point of the device, wherein the timestamp of the packet is stored in a correction field of the packet;
updating the timestamp of the packet with the residence time of the packet, wherein updating the timestamp of the packet comprises updating the correction field of the packet;
recalculating a checksum of the packet; and
transmitting the packet out of the egress point of the apparatus to a second device.
10. The computer readable medium of claim 9, wherein the actions further comprise verifying the checksum of the packet.
11. The computer readable medium of claim 9, wherein the egress point of the packet is between a media independent interface layer and a physical layer of the apparatus.