1. A centrifugal fan, comprising:
a housing;
a circular base;
a driving mechanism, mounted on the circular base;
at least two support brackets, linking the circular base to the housing, the support bracket profiles are involute curves based upon the circular base; and
multiple centrifugal impellers, driven by the driving mechanism and sucking airflow into the housing through void spaces among the support brackets,
wherein the involute curves are generated according to the equation V=Lei\u03b8, wherein:
L=R(1+t2)0.5;
\u03b8=t\u2212tan\u22121(t);
V being an involute curve;
L being the distance between a point of the involute curve and a center of the circular base;
R being the radius of the circular base;
T being a parameter from zero to infinity; and
\u03b8 being an angle between an initial line and a line, linking the point of the involute curve and the center of the circular base.
2. The centrifugal fan of claim 1, wherein the driving mechanism is a motor.
3. A centrifugal fan, comprising:
a housing;
a circular base;
a driving mechanism, mounted on the circular base;
at least two support brackets, linking the circular base to the housing, the support bracket profiles are involute curves based upon the circular base; and
multiple centrifugal impellers are driven by the driving mechanism and suck airflow into the housing through void spaces among the support brackets, the centrifugal impellers are perpendicular to the support bracket profiles,
wherein the involute curves are generated according to the equation V=Lei\u03b8, wherein:
L=R(1+t2)0.5;
\u03b8=t\u2212tan\u22121(t);
V being an involute curve;
L being the distance between a point of the involute curve and a center of the circular base;
R being the radius of the circular base;
T being a parameter from zero to infinity; and
\u03b8 being an angle between an initial line and a line, linking the point of the involute curve and the center of the circular base.
4. The centrifugal fan of claim 3, wherein the driving mechanism is a motor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit, comprising:
a semiconductor substrate, the substrate having a first conductivity type;
an epitaxial layer disposed on a top surface of the substrate, the epitaxial layer having the same conductivity type as sais substrate; and
an extended drain metal oxide semiconductor (MOS) transistor, the extended drain MOS transistor further including:
a drift layer disposed in the epitaxial layer, the drift layer having an opposite conductivity type from the substrate, and the drift layer contacting a drain diffused contact region and abutting a channel region of the extended drain MOS transistor;
an upper RESURF layer disposed in the epitaxial layer over the drift layer, so that the upper RESURF layer contacts a top surface of the drift layer, the upper RESURF layer having the same conductivity type as the substrate; and
a buried drain extension disposed in the substrate, so that the buried drain extension is electrically connected to the drift layer proximate to the drain diffused contact region and separated from the drift layer proximate to the channel region, the buried drain extension having the opposite conductivity type from the substrate.
2. The integrated circuit of claim 1, wherein a local average doping density of the upper RESURF layer proximate to the channel region is between 1\xd71016 cm\u22123 and 5\xd71017 cm\u22123, and a local average doping density of the upper RESURF layer proximate to the drain diffused contact region is between 5 and 20 times lower than the local average doping density of the upper RESURF layer proximate to the channel region.
3. The integrated circuit of claim 1, wherein a local average doping density of the drift layer proximate to the drain diffused contact region is between 5\xd71015 cm\u22123 and 5\xd71016 cm\u22123, and a local average doping density of the drift layer proximate to the channel region is between 5 and 20 times lower than the local average doping density of the drift layer proximate to the drain diffused contact region.
4. The integrated circuit of claim 1, wherein a local average doping density of the buried drain extension proximate to the drain diffused contact region is between 5\xd71015 cm\u22123 and 5\xd71016 cm\u22123, and a local average doping density of the buried drain extension proximate to the channel region is between 5 and 20 times lower than the local average doping density of the buried drain extension proximate to the drain diffused contact region.
5. The integrated circuit of claim 1, wherein the extended drain MOS transistor further includes a lower RESURF layer disposed between the drift layer and the buried drain extension, the lower RESURF layer having the same conductivity type as the substrate.
6. The integrated circuit of claim 5, wherein a local average doping density of the lower RESURF layer proximate to the channel region is between 1\xd71015 cm\u22123 and 1\xd71017 cm\u22123, and a local average doping density of the lower RESURF layer proximate to the drain diffused contact region is between 5 and 20 times lower than the local average doping density of the lower RESURF layer proximate to the channel region.
7. The integrated circuit of claim 1, wherein:
the buried drain extension is electrically contiguous and extends below a source region of the extended drain MOS transistor; and
the drift layer includes an isolating extension contacting the buried drain extension and laterally surrounding a backgate well of the extended drain MOS transistor so as to electrically isolate the backgate well.
8. The integrated circuit of claim 1, further including a drain link between the drift layer and the buried drain extension proximate to the drain diffused contact region, the drain link having the opposite conductivity type from the substrate, so that the drift layer is electrically connected to the buried drain extension through the drain link.
9. The integrated circuit of claim 1, wherein the extended drain MOS transistor further includes an immersed RESURF layer disposed in the drift layer at a depth between one third and two thirds of a depth of the drift layer so that the drift layer extends above and below the immersed RESURF layer, the immersed RESURF layer having the same conductivity type as the substrate.
10. A method of forming an integrated circuit, comprising steps:
providing a semiconductor substrate, the substrate having a first conductivity type;
forming a buried drain extension implant mask over a top surface of the substrate, so as to expose the top surface of the substrate in an area defined for a buried drain extension;
performing a buried drain extension ion implant process on the integrated circuit to form a buried drain extension implanted layer in the substrate;
performing a thermal drive operation on the integrated circuit so as to diffuse dopants in the buried drain extension implanted layer outward to form a partially diffused buried drain extension;
forming an epitaxial layer on the top surface of the substrate, the epitaxial layer having the same conductivity type as the substrate, so that dopants in the partially diffused buried drain extension diffuse outward to form a buried drain extension, the buried drain extension having an opposite conductivity type from the substrate;
forming a drift layer implant mask over a top surface of the epitaxial layer, so as to expose the top surface of the epitaxial layer in an area defined for a drift layer;
performing a drift layer ion implant process on the integrated circuit to form a drift implanted layer in the substrate;
performing a thermal drive operation on the integrated circuit so as to diffuse dopants in the drift implanted layer outward to form a drift layer, the drift layer having the opposite conductivity type from the substrate, so that the drift layer is electrically connected to the buried drain extension at a drain end of the drift layer and is separated from the buried drain extension at a channel end of the drift layer;
forming a dielectric layer at the top surface of the epitaxial layer over the drift layer, so as to leave exposed a portion at the drain end of the drift layer and a portion at the channel end of the drift layer;
forming an upper RESURF layer implant mask over a top surface of the dielectric layer, so as to expose the top surface of the dielectric layer in an area defined for an upper RESURF layer;
performing an upper RESURF layer ion implant process on the integrated circuit to form an upper RESURF implanted layer in the epitaxial layer below the dielectric layer;
performing an anneal operation on the integrated circuit so as to diffuse dopants in the upper RESURF implanted layer outward to form an upper RESURF layer, the upper RESURF layer having the same conductivity type as the substrate, so that a bottom surface of the upper RESURF layer contacts the drift layer;
forming a gate over a channel region of the extended drain MOS transistor, the channel region being located adjacent to the channel end of the drift layer;
forming a channel side field plate over the dielectric layer adjacent to the gate; and
forming a drain side field plate over the dielectric layer proximate to the drain end of the drift layer.
11. The method of claim 10, wherein:
a local average doping density of the upper RESURF layer proximate to the channel region is between 1\xd71016 cm\u22123 and 5\xd71017 cm\u22123; and
the upper RESURF layer implant mask includes blocking elements so that a local average doping density of the upper RESURF layer proximate to the drain diffused contact region is between 5 and 20 times lower than the local average doping density of the upper RESURF layer proximate to the channel region.
12. The method of claim 10, wherein:
a local average doping density of the drift layer proximate to the drain diffused contact region is between 5\xd71015 cm\u22123 and 5\xd71016 cm\u22123; and
the drift layer implant mask includes blocking elements so that a local average doping density of the drift layer proximate to the channel region is between 5 and 20 times lower than the local average doping density of the drift layer proximate to the drain diffused contact region.
13. The method of claim 10, wherein:
a local average doping density of the buried drain extension proximate to the drain diffused contact region is between 5\xd71015 cm\u22123 and 5\xd71016 cm\u22123; and
the buried drain extension implant mask includes blocking elements so that a local average doping density of the buried drain extension proximate to the channel region is between 5 and 20 times lower than the local average doping density of the buried drain extension proximate to the drain diffused contact region.
14. The method of claim 10, further including steps:
forming a lower RESURF layer implant mask over a top surface of the substrate so as to expose the top surface of the substrate in an area defined for a lower RESURF layer, prior to the step of forming the epitaxial layer and subsequent to the step of performing the thermal drive operation on to form the partially diffused buried drain extension; and
subsequently performing a lower RESURF layer ion implant process on the integrated circuit to form a lower RESURF implanted layer in the substrate, so that:
the step of forming the epitaxial layer results in dopants in the lower RESURF implanted layer diffusing outward to form a lower RESURF layer having the same conductivity type as the substrate;
a bottom surface of the lower RESURF layer contacts a top surface of the buried drain extension; and
a bottom layer of the drift layer contacts a top surface of the lower RESURF layer.
15. The method of claim 14, wherein:
a local average doping density of the lower RESURF layer proximate to the channel region is between 1\xd71015 cm\u22123 and 1\xd71017 cm\u22123; and
the lower RESURF layer implant mask includes blocking elements so that a local average doping density of the lower RESURF layer proximate to the drain diffused contact region is between 5 and 20 times lower than the local average doping density of the lower RESURF layer proximate to the channel region.
16. The method of claim 15, wherein:
the extended drain MOS transistor a linear portion and a rounded portion;
the lower RESURF layer implant mask has linear exposed areas in the linear portion which are spaced at a first set of intervals; and
the lower RESURF layer implant mask has rounded exposed areas in the rounded portion which are spaced at a second set of intervals, such that some members of the first set of intervals are not equal to corresponding members of the second set of intervals.
17. The method of claim 10, wherein:
the buried drain extension is electrically contiguous and extends below a source region of the extended drain MOS transistor; and
the drift layer includes an isolating extension contacting the buried drain extension and laterally surrounding a backgate well of the extended drain MOS transistor so as to electrically isolate the backgate well.
18. The method of claim 10, further including steps:
forming a drain link implant mask over a top surface of the epitaxial layer so as to expose the top surface of the epitaxial layer in an area defined for a drain link, prior to the step of performing the thermal drive operation on to form the drift layer; and
subsequently performing a drain link ion implant process on the integrated circuit to form a drain link implanted layer in the substrate, so that:
the step of performing the thermal drive to form the drift layer results in dopants in the drain link implanted layer diffusing outward to form a drain link having the opposite conductivity type from the substrate;
the drain link overlaps the drift layer and the buried drain extension; and
the drift layer and the buried drain extension are electrically connected through the drain link.
19. The method of claim 10, wherein:
the upper RESURF layer implant mask exposes an area for a channel stop implanted layer in a low voltage MOS transistor area of the integrated circuit; and
the step of performing the upper RESURF layer ion implant process forms the channel stop implanted layer in the epitaxial layer in the low voltage MOS transistor area.
20. The method of claim 10, further including steps:
forming an immersed RESURF implant mask over a top surface of the epitaxial layer so as to expose the top surface of the epitaxial layer in an area defined for an immersed RESURF layer;
performing an immersed RESURF ion implant process on the integrated circuit to form an immersed RESURF implanted layer in the epitaxial layer; and
performing an anneal operation on the integrated circuit so that:
dopants in the immersed RESURF implanted layer diffuse outward to form an immersed RESURF layer having the same conductivity type as the substrate;
the immersed RESURF layer is at a depth between one third and two thirds of a depth of the drift layer; and
the drift layer extends above and below the immersed RESURF layer.