What is claimed is:
1. A compound 8 to 50 nucleobases in length targeted to a nucleic acid molecule encoding apolipoprotein B, wherein said compound specifically hybridizes with and inhibits the expression of a nucleic acid molecule encoding apolipoprotein B.
2. The compound of claim 1 which is an antisense oligonucleotide.
3. The compound of claim 2 wherein the antisense oligonucleotide has a sequence comprising SEQ ID NO: 17, 18, 19, 20, 21, 23, 24, 25, 27, 28, 30, 31, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 45, 46, 48, 49, 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 66, 67, 69, 71, 73, 74, 75, 76, 78, 79, 81, 82, 83, 84, 86, 87, 88, 90, 93, 96, 101, 101, 102, 103, 105, 109, 111, 111, 114, 115, 116, 117, 118, 119, 120, 121 or 122.
4. The compound of claim 2 wherein the antisense oligonucleotide comprises at least one modified internucleoside linkage.
5. The compound of claim 4 wherein the modified internucleoside linkage is a phosphorothioate linkage.
6. The compound of claim 2 wherein the antisense oligonucleotide comprises at least one modified sugar moiety.
7. The compound of claim 6 wherein the modified sugar moiety is a 2-O-methoxyethyl sugar moiety.
8. The compound of claim 2 wherein the antisense oligonucleotide comprises at least one modified nucleobase.
9. The compound of claim 8 wherein the modified nucleobase is a 5-methylcytosine.
10. The compound of claim 2 wherein the antisense oligonucleotide is a chimeric oligonucleotide.
11. A compound 8 to 50 nucleobases in length which specifically hybridizes with at least an 8-nucleobase portion of an active site on a nucleic acid molecule encoding apolipoprotein B.
12. A composition comprising the compound of claim 1 and a pharmaceutically acceptable carrier or diluent.
13. The composition of claim 12 further comprising a colloidal dispersion system.
14. The composition of claim 12 wherein the compound is an antisense oligonucleotide.
15. A method of inhibiting the expression of apolipoprotein B in cells or tissues comprising contacting said cells or tissues with the compound of claim 1 so that expression of apolipoprotein B is inhibited.
16. A method of treating an animal having a disease or condition associated with apolipoprotein B comprising administering to said animal a therapeutically or prophylactically effective amount of the compound of claim 1 so that expression of apolipoprotein B is inhibited.
17. The method of claim 16 wherein the condition involves abnormal lipid metabolism.
18. The method of claim 16 wherein the condition involves abnormal cholesterol metabolism.
19. The method of claim 16 wherein the condition is atherosclerosis.
20. The compound of claim 1 targeted to a nucleic acid molecule encoding apolipoprotein B, wherein said compound specifically hybridizes with and inhibits the expression of the long form of a nucleic acid molecule encoding apolipoprotein B, ApoB-100.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A compression test circuit of a memory device, comprising:
a plurality of banks each comprising a plurality of bit line sense amplifiers for sensing and amplifying data in bit lines;
a plurality of inputoutput amplifiers to amplify data which is amplified by the bit line sense amplifier and is loaded in inputoutput lines;
a plurality of compression comparators for compressing and comparing data amplified by the plurality of inputoutput amplifiers in each bank;
a plurality of global inputoutput drivers for driving each data amplified by the plurality of inputoutput amplifiers or for driving each of a plurality of comparison signals outputted from the plurality of compression comparators;
a plurality of output drivers for driving data driven by the global inputoutput driving unit to an external pin; and
an inputoutput amplification control unit for generating a plurality of first control signals to activate the plurality of inputoutput amplifiers in each bank at different timings in a test mode.
2. The compression test circuit according to claim 1, wherein the inputoutput amplification control unit comprises:
a reference signal generating unit for generating a reference signal in response to a read mode signal; and
a control signal generating unit for generating the plurality of first control signals in response to a plurality of delay signals each obtained by delaying the reference signal for a different delay time in the test mode.
3. The compression test circuit according to claim 2, wherein the reference signal generating unit includes a pulse generator.
4. The compression test circuit according to claim 2, wherein the control signal generating unit comprises:
a normal operation control unit for controlling the plurality of first control signals to have the same logic state as that of the reference signal in response to the reference signal and the test mode signal in a normal operation; and
a test operation control unit for controlling the plurality of first control signals each to have a different activation point in response to the delay signal and the test mode signal in the test mode.
5. The compression test circuit according to claim 4, wherein the test operation control unit includes a plurality of delay units each for delaying the reference signal for a different delay time to generate a plurality of delay signals.
6. The compression test circuit according to claim 1, wherein one or more in each bank of the plurality of global inputoutput drivers drive data amplified by the plurality of inputoutput amplifiers or drive a plurality of comparison signals outputted from the plurality of compression comparators.
7. The compression test circuit according to claim 6, further comprising a global inputoutput driving control unit for activating the predetermined number of global inputoutput drivers at a different activation point in the test mode.
8. The compression test circuit according to claim 7, wherein the global inputoutput driving control unit comprises:
a normal driving signal generating unit for generating a normal driving signal to activate the plurality of global inputoutput drivers connected the selected bank in response to the first control signal and the test mode signal in a normal mode; and
a test driving signal generating unit for generating a plurality of test driving signals to activate the predetermined number of global inputoutput drivers at a different activation point in response to the first control signal and the test mode signal in the test mode.
9. The compression test circuit according to claim 8, wherein the test driving signal generating unit includes a plurality of delay units each obtained by delaying the first control signal for a different delay time to generate a plurality of delay signals.
10. A compression test circuit of a memory device, comprising:
a plurality of banks each comprising a plurality of bit line sense amplifiers for sensing and amplifying data in bit lines;
a plurality of inputoutput amplifiers to amplify data which is amplified by the bit line sense amplifier and is loaded in inputoutput lines;
a plurality of compression comparators for compressing and comparing data amplified by the plurality of inputoutput amplifiers in each bank;
a plurality of global inputoutput drivers for driving each data amplified by the plurality of inputoutput amplifiers or driving each of a plurality of comparison signals outputted from the plurality of compression comparators;
a plurality of output drivers for driving data driven by the global inputoutput driving unit to an external pin; and
an inputoutput amplification control unit for generating a plurality of first control signals to activate the plurality of inputoutput amplifiers connected to each bank in a test mode by a plurality of groups at different timings.
11. The compression test circuit according to claim 10, wherein the inputoutput amplification control unit comprises:
a reference signal generating unit for generating a reference signal in response to a read mode signal; and
a control signal generating unit for generating the plurality of first control signals in response to a plurality of delay signals each for delaying the reference signal for a different delay time in the test mode.
12. The compression test circuit according to claim 11, wherein the reference signal generating unit includes a pulse generator.
13. The compression test circuit according to claim 11, wherein the control signal generating unit comprises:
a normal operation control unit for controlling the plurality of first control signals to have the same logic state as that of the reference signal in response to the reference signal and the test mode signal in a normal operation; and
a test operation control unit for controlling the plurality of first control signals to have different activation points in response to the delay signal and the test mode signal in the test mode.
14. The compression test circuit according to claim 13, wherein the test operation control unit includes a plurality of delay units each for delaying the reference signal for a different delay time to generate the plurality of delay signals.
15. The compression test circuit according to claim 10, wherein one or more in each bank of the plurality of global inputoutput drivers drive data amplified by the plurality of inputoutput amplifiers or drive a plurality of comparison signals outputted from the plurality of compression comparators.
16. The compression test circuit according to claim 15, further comprising a global inputoutput driving control unit for activating the predetermined number of global inputoutput drivers at a different activation point in the test mode.
17. The compression test circuit according to claim 16, wherein the global inputoutput driving control unit comprises:
a normal driving signal generating unit for generating a normal driving signal to activate the plurality of global inputoutput drivers connected to the selected bank in response to the first control signal and the test mode signal in a normal mode; and
a test driving signal generating unit for generating a plurality of test driving signals to activate the predetermined number of global inputoutput drivers at a different activation point in response to the first control signal and the test mode signal in the test mode.
18. The compression test circuit according to claim 17, wherein the test driving signal generating unit includes a plurality of delay units each for delaying the first control signal for a different delay time to generate a plurality of delay signals.