1. A method for configuring an integrated circuit (IC) comprising:
determining a multi-bit configuration value on a single node by at least using both a voltage level at the single node and detecting a time to reach a voltage threshold level at the single node based on a voltage ramp generation circuit; and
configuring an operation mode of a circuit in the IC based on the determined multi-bit configuration value from the single node.
2. The method of claim 1 comprising determining the multi-bit configuration value on the single node prior to the IC coming out of a reset mode and detecting the voltage level based on resistor divider circuit.
3. The method of claim 2 comprising determining a plurality of configuration bits based on converting an analog voltage to digital value obtained from the resistor divider and determining a plurality of configuration bits based on a threshold voltage and a time determined to charge the capacitor circuit of the RC network, prior to the IC coming out of reset.
4. The method of claim 3 comprising:
providing a clock source independent of a clock source of the circuit in the IC.
5. The method of claim 1 comprising determining at least a first configuration bit at the single node based on the voltage level and at least a second configuration bit at the single node based on an RC network.
6. A method for configuring an integrated circuit (IC) comprising:
determining a multi-bit configuration value on a single node by at least using both a current level at the single node and detecting a time to reach a voltage threshold level at the single node based on a time to reach a voltage threshold level generator circuit; and
configuring an operation mode of a circuit in the IC based on the determined multi-bit configuration value from the single node.
7. The method of claim 6 comprising determining the multi-bit configuration value on the single node prior to the IC coming out of a reset mode and detecting the current level based on current sink circuit.
8. The method of claim 6 comprising determining at least a first configuration bit at the single node based on the current level and at least a second configuration bit at the single node based in a RC network.
9. An apparatus comprising:
an integrated circuit that comprises:
at least one configurable circuit; and
at least one single node multi-bit configuration port that comprises configuration detection logic operative to determine a multi-bit configuration value on a single node by at least using both a voltage level at the single node and detecting a time to reach a voltage threshold level at the single node based on a voltage ramp generation circuit; and wherein the integrated circuit configures an operation mode of the at least one configurable circuit in the IC based on the determined multi-bit configuration value from the single node.
10. The apparatus of claim 9 comprising:
multi-bit configuration logic, operatively coupled to the single node, comprising a voltage divider circuit and the time to reach a voltage threshold level generation circuit, and wherein the time to reach a voltage threshold level generation circuit comprises a resistor capacitor (RC) network; and
wherein the configuration detection logic is operative to determine the multi-bit configuration value prior to the IC coming out of a reset mode.
11. The apparatus of claim 10 wherein the voltage divider circuit is located off die from the integrated circuit and wherein a capacitor circuit of the RC network is located off die from the IC and wherein the configuration detection logic is operative to generate the multi-bit configuration value having a set of most significant bits generated based on the voltage level and a set of least significant bits generated based on the detected time to reach a voltage threshold level.
12. The apparatus of claim 9 wherein the configuration detection logic is operative to determine at least a first configuration bit at the single node based on the voltage level and at least a second configuration bit at the single node based on a RC network.
13. The apparatus of claim 10 wherein the configuration detection logic comprises an analog to digital converter circuit and is operative to determine a plurality of configuration bits based on converting an analog voltage to digital value obtained from the voltage divider circuit and logic operative to determine a plurality of configuration bits based on converting an analog voltage to digital voltage obtained based on a threshold voltage and a time determined to charge the capacitor circuit of the RC network, prior to the IC coming out of reset.
14. The apparatus of claim 13 comprising a clock source independent of a clock source of the circuit in the IC wherein the configuration detection logic is operative to select different voltage levels corresponding to different bits of the plurality of configuration bits on the single node based on the clock signals from the clock source.
15. The apparatus of claim 9 comprising inputoutput logic coupled to the single node.
16. The apparatus of claim 9 comprising a display operatively coupled to the integrated circuit.
17. The apparatus of claim 9 comprising a plurality of single node multi-bit configuration ports, each coupled to a corresponding node and that each comprise configuration detection logic operative to determine a multi-bit configuration value on a respective single node by at least using both a voltage level at the single node and detecting a time to reach a voltage threshold level at the single node based on a time to reach a voltage threshold level generation circuit; and configure an operation mode of a circuit in the IC based on the determined multi-bit configuration value from the single node.
18. A non-transitory computer readable storage medium comprising executable instructions that when executed cause an integrated circuit fabrication system to produce an integrated circuit comprising:
at least one single node multi-bit configuration port that comprises configuration detection logic operative to determine a multi-bit configuration value on a single node by at least using both a voltage level at the single node and detecting a time to reach a voltage threshold level at the single node based on a time to reach a voltage threshold level generation circuit; and
configure an operation mode of a circuit in the IC based on the determined multi-bit configuration value from the single node.
19. The computer readable medium of claim 18 comprising executable instructions that when executed cause an integrated circuit fabrication system to produce an integrated circuit wherein the configuration detection logic is operative to determine at least a first configuration bit at the single node based on the voltage level and at least a second configuration bit at the single node based on the time to reach a voltage threshold level from a time to reach a voltage threshold level generation circuit.
20. The apparatus of claim 18 comprising executable instructions that when executed cause an integrated circuit fabrication system to produce an integrated circuit wherein the configuration detection logic comprises an analog to digital converter circuit and is operative to determine a plurality of configuration bits based on converting an analog voltage to digital voltage obtained from the voltage level at the single node and determining a plurality of configuration bits based on converting an analog voltage to digital voltage obtained based on a threshold voltage and a time determined to charge a capacitor circuit of an resistor capacitor network, prior to the IC coming out of reset.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of fabricating a thin film transistor, comprising:
providing a first base;
forming a gate on the first base;
forming a dielectric layer on the first base;
forming a metal-oxide semiconductor channel on the first base, the metal-oxide semiconductor channel comprising a metal-oxide semiconductor layer and a plurality of nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another; and
forming a source and a drain on the first base, wherein the gate and the metal-oxide semiconductor channel are overlapped, the gate, the source, and the drain are separated by the dielectric layer, and the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel.
2. The method as recited in claim 1, wherein the nano micro structures are a plurality of nano particles.
3. The method as recited in claim 2, wherein the step of forming the metal-oxide semiconductor channel on the first base comprises:
placing the nano particles on the first base; and
forming the metal-oxide semiconductor layer on the nano particles to cover the nano particles.
4. The method as recited in claim 2, wherein the step of forming the metal-oxide semiconductor channel on the first base comprises:
providing the nano particles;
providing a metal-oxide semiconductor precursor;
mixing the nano particles and the metal-oxide semiconductor precursor to form a mixed solution; and
solidifying the mixed solution on the first base to form the metal-oxide semiconductor channel.
5. The method as recited in claim 2, wherein carrier concentration of the nano particles is greater than carrier concentration of the metal-oxide semiconductor layer.
6. The method as recited in claim 1, wherein each of the nano micro structures is a nano pore, and inner walls of the nano pores are conductive.
7. The method as recited in claim 6, wherein the step of forming the metal-oxide semiconductor channel on the first base comprises:
forming a metal-oxide semiconductor pre-channel on the first base, the metal-oxide semiconductor pre-channel comprising the metal-oxide semiconductor layer and the nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another;
removing the nano particles in the metal-oxide semiconductor layer to form the nano pores; and
performing surface treatment on the inner walls of the nano pores to effect conductivity of the inner walls of the nano pores.
8. The method as recited in claim 7, wherein the step of removing the nano particles in the metal-oxide semiconductor layer comprises:
removing the nano particles in the metal-oxide semiconductor layer by means of an adhesive, a solvent, or plasma.
9. The method as recited in claim 7, wherein the step of performing the surface treatment on the inner walls of the nano pores to effect the conductivity of the inner walls of the nano pores comprises:
performing the surface treatment on the inner walls of the nano pores by means of plasma, a reactive gas, ultraviolet light, or a reactive liquid.
10. The method as recited in claim 7, wherein a material of the nano particles is organic.
11. A thin film transistor comprising:
a gate;
a dielectric layer;
a metal-oxide semiconductor channel comprising a metal-oxide semiconductor layer and a plurality of nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another; and
a source and a drain, wherein the gate and the metal-oxide semiconductor channel are overlapped, the gate, the source, and the drain are separated by the dielectric layer, and the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel.
12. The thin film transistor as recited in claim 11, wherein the nano micro structures are a plurality of nano particles.
13. The thin film transistor as recited in claim 12, wherein carrier concentration of the nano particles is greater than carrier concentration of the metal-oxide semiconductor layer.
14. The thin film transistor as recited in claim 11, wherein a material of the metal-oxide semiconductor layer comprises aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium-gallium-zinc oxide (IGZO), indium gallium oxide (IGO), zinc oxide (ZnO), cadmium oxide\u2022germanium dioxide (2CdO\u2022GeO2), or nickel cobalt oxide (NiCo2O4), and a material of the nano micro structures comprises ITO or IZO.
15. The thin film transistor as recited in claim 11, wherein each of the nano micro structures is a nano pore, and inner walls of the nano pores are conductive.
16. A display panel comprising:
a thin film transistor array substrate comprising:
a first base; and
a plurality of thin film transistors arranged in arrays on the first base, each of the thin film transistors comprising:
a gate;
a dielectric layer;
a metal-oxide semiconductor channel comprising a metal-oxide semiconductor layer and a plurality of nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another; and
a source and a drain, wherein the gate and the metal-oxide semiconductor channel are overlapped, the gate, the source, and the drain are separated by the dielectric layer, and the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel;
an opposite substrate disposed opposite to the thin film transistor array substrate; and
a display medium disposed between the thin film transistor array substrate and the opposite substrate.
17. The display panel as recited in claim 16, wherein the nano micro structures are a plurality of nano particles.
18. The display panel as recited in claim 17, wherein carrier concentration of the nano particles is greater than carrier concentration of the metal-oxide semiconductor layer.
19. The display panel as recited in claim 16, wherein a material of the metal-oxide semiconductor layer comprises aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium-gallium-zinc oxide (IGZO), indium gallium oxide (IGO), zinc oxide (ZnO), cadmium oxide\u2022germanium dioxide (2CdO\u2022GeO2), or nickel cobalt oxide (NiCo2O4), and a material of the nano micro structures comprises ITO or IZO.
20. The display panel as recited in claim 16, wherein each of the nano micro structures is a nano pore, and inner walls of the nano pores are conductive.