1. A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns,
wherein each of the non-volatile memory devices has:
a word gate formed above a semiconductor layer with a gate insulating layer interposed;
an impurity layer formed in the semiconductor layer to form a source region or a drain region; and
control gates in the form of side walls formed along both side surfaces of the word gate,
wherein each of the control gates consists of a first control gate and a second control gate adjacent to each other;
wherein a first insulating layer which is a stack of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film is disposed between the first control gate and the semiconductor layer, and a side insulating layer is disposed between the first control gate and the word gate;
wherein a second insulating layer which is formed of a silicon oxide film is disposed between the second control gate and the semiconductor layer; and
wherein the thickness of the silicon oxide film of the second insulating layer is less than the thickness of the first silicon oxide film of the first insulating layer.
2. The semiconductor device as defined in claim 1,
wherein an end surface of the first insulating layer on the side of the second insulating layer is covered by a charge transfer protection film.
3. The semiconductor device as defined in claim 2,
wherein the charge transfer protection film is one of a silicon oxide film and a silicon nitride oxide film.
4. The semiconductor device as defined in claim 1,
wherein a sidewall formed of a charge transfer protection film is formed on an end surface of the first insulating layer on the side of the second insulating layer.
5. The semiconductor device as defined in claim 4,
wherein the charge transfer protection film is one of a silicon oxide film and a silicon nitride oxide film.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A pixel processing method comprising:
inserting pixel surface texture attribute values in a payload portion of a pixel packet row, wherein said texture attribute values correspond to an address of one of a plurality of concurrently existing subtables embodied in a tangible computer readable medium wherein at least two of said plurality of concurrently existing subtables have a different length, wherein each sub-table comprises a range having a start address and a length and wherein said start address is a multiple of m and wherein each range is of a length addressable by y-bits; and a sub-table index value of x-bits, wherein said address is computed by multiplying said sub-table index value by m and adding to the result thereof said texture index value; and
forwarding said pixel packet row for processing associated with a graphical presentation.
2. A pixel processing method as described in claim 1 wherein m is 16.
3. A pixel processing method as described in claim 1 wherein y is 8-bits.
4. A pixel processing method as described in claim 1 wherein y is 4-bits.
5. A pixel processing method as described in claim 1 wherein x is 4-bits.
6. A pixel processing method as described in claim 1 wherein said palette memory outputs a 16-bit value and is addressed by an 8-bit value, a, and wherein m is 16 and x is 4-bits.
7. A pixel processing method as described in claim 6 wherein y is 4-bits.
8. A pixel processing method as described in claim 6 wherein y is 8-bits.
9. A pixel processing method of claim 1 wherein said address is determined by utilizing a texel index that provides an index into a texture palette table of arbitrary size with different lengths from another concurrently existing texture palette table in a texture palette storage embodied in a tangible computer readable medium; and an offset into the texture palette storage, wherein the offset describes an offset of the texture palette table of arbitrary size in the texture palette storage, and said offset is padded with additional bits;
adding the texel index to the offset to obtain a texture palette storage index with an adder component; and
accessing a texel value in the texture palette storage for use in rendering pixels, based on the texture palette storage index.
10. A pixel processing method comprising:
accessing a texel index, wherein said texel index provides an index into a texture palette table of arbitrary size with different lengths from another concurrently existing texture palette table in a texture palette storage embodied in a computer readable medium;
accessing an offset into the texture palette storage, wherein the offset describes an offset of the texture palette table of arbitrary size in the texture palette storage, and said offset is padded with additional bits;
combining by adding the texel index to the offset to obtain a texture palette storage index with an adder component, wherein at least one bit of the texel index is masked prior to said combining the texel index to the offset to obtain the texture palette storage index;
accessing a texel value in the texture palette storage based on the texture palette storage index;
inserting said texel value in a pixel packet; and
processing said pixel packet in a graphics pipeline.