1. (canceled)
2. An amplifier circuit, comprising:
a first transistor having a control terminal that receives a first amplifier input, a first terminal, and a second terminal;
a transimpedance amplifier having an input that is directly connected to the first terminal of the first transistor, and an output; and
an output amplifier having an input that is connected to the output of the transimpedance amplifier and an output.
3. The amplifier circuit of claim 2 further comprising a first load that is connected to the first terminal of the first transistor.
4. The amplifier circuit of claim 2 further comprising a current source that is connected to the second terminal of the first transistor.
5. The amplifier circuit of claim 2 wherein the transimpedance amplifier comprises a nested transimpedance amplifier.
6. The amplifier circuit of claim 2 wherein the output amplifier comprises an operational amplifier.
7. The amplifier circuit of claim 2 wherein the output amplifier comprises a telescopic cascoded amplifier.
8. The amplifier circuit of claim 7 wherein the telescopic cascoded amplifier comprises:
an input transistor having a control terminal that is connected to the output of the transimpedance amplifier, a first terminal, and a second terminal;
an output transistor having a first terminal that is connected to the second terminal of the input transistor, a control terminal, and a second terminal that is connected to the output of the output amplifier; and
an output current source that is connected to the second terminal of the output transistor.
9. The amplifier circuit of claim 2 wherein the output amplifier comprises a push-pull amplifier.
10. An analog-to-digital converter (ADC) comprising N cascaded ADC stages, where N is a integer, wherein at least one of the cascaded ADC stages comprises the amplifier circuit of claim 2.
11. An amplifier circuit comprising:
a first transistor having a control terminal that receives a first amplifier input, a first terminal, and a second terminal;
a second transistor having a control terminal that receives a second amplifier input, a first terminal, and a second terminal that is connected to the second terminal of the first transistor;
a differential transimpedance amplifier having a first input that is directly connected to the first terminal of the first transistor, a second input that is directly connected to the first terminal of the second transistor, a first output, and a second output; and
a differential output amplifier having a first input that is connected to the first output of the differential transimpedance amplifier, a second input that is connected to the second output of the differential transimpedance amplifier, a first output, and a second output.
12. The amplifier circuit of claim 11 further comprising a second load that is connected to the first terminal of the second transistor.
13. The amplifier circuit of claim 11 wherein the differential transimpedance amplifier comprises a nested differential transimpedance amplifier.
14. The amplifier circuit of claim 11 wherein the differential output amplifier comprises a differential operational amplifier.
15. The amplifier circuit of claim 11 wherein the differential output amplifier comprises a differential telescopic cascoded amplifier.
16. The amplifier circuit of claim 11 wherein the differential output amplifier comprises a differential push-pull amplifier.
17. An analog-to-digital converter (ADC) comprising N cascaded ADC stages, where N is a integer, wherein at least one of the cascaded ADC stages comprises the amplifier circuit of claim 11.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A logic device with reduced leakage current, comprising:
an array of logic devices;
a switch connected between each supply terminal and each virtual supply terminal of said logic devices for sourcingsinking current tofrom said logic devices; and
voltage controlled constriction devices connected between said supply terminals and said virtual supply terminals, said voltage controlled constriction devices being biased by reference voltages between less than a supply voltage and more than a ground voltage to reduce the leakage current in an area efficient manner.
2. The logic device with reduced leakage current as in claim 1 wherein said logic device includes circuitry selected from the group consisting of memory cells, SRAM based content addressable memory, and bitline precharge circuitry.
3. The logic device with reduced leakage current as in claim 1 wherein said constriction devices are biased from the reference voltages whose levels are variably controlled.
4. A logic device with reduced leakage current, comprising:
an array of logic devices;
a switch connected between each supply terminal and each virtual supply terminal of said logic devices for sourcingsinking current tofrom said logic devices; and
voltage controlled constriction devices connected between said supply terminals and said virtual supply terminals, said voltage controlled constriction devices being biased to reduce the leakage current in an area efficient manner;
wherein said constriction devices are biased from diodesdiode connected transistors connected between said supply terminals and gates of said constriction devices, and a temperature tracking mechanism connected between said diodesdiode connected transistors.
5. The logic device with reduced leakage current as in claim 4 wherein said temperature-tracking mechanism includes a reference logic cell array.
6. The logic device with reduced leakage current as in claim 1 wherein said constriction devices comprise:
a small-sized PMOS transistor connected between said supply terminals and said virtual supply terminals of said logic devices;
a small-sized NMOS transistor connected between said supply terminals and said virtual supply terminals of said logic devices;
thereby providing constriction in the path of supply to said logic devices.
7. The logic device with reduced leakage current as in claim 1 wherein a decoupling capacitance is provided with said supply terminals of said logic devices to provide stable supplysink in normal operation.
8. A logic device with reduced leakage current, comprising:
an array of logic devices;
a switch connected between each supply terminal and each virtual supply terminal of said logic devices for sourcingsinking current to said logic devices;
voltage controlled constriction devices connected between said supply terminals and said virtual supply terminals;
said voltage controlled constriction devices being biased from:
diodesdiode connected transistors connected between said supply terminals and gates of said constriction devices; and
a temperature tracking mechanism connected between said diodesdiode connected transistors, to thereby reducing the leakage current in an area efficient manner.
9. An integrated circuit, comprising:
logic circuitry coupled to a virtual ground; and
a ground constriction circuit coupled between the virtual ground and a ground reference, the ground constriction circuit including a first transistor sourcedrain coupled between the virtual ground and ground reference and having a gate terminal coupled to receive a first control signal having a voltage between but not equal to either a supply reference and the ground reference that changes an amount of current sourced by the first transistor.
10. The integrated circuit of claim 9 wherein the logic circuitry is coupled between the virtual ground and a virtual supply, further comprising a decoupling capacitance defining the virtual supply and virtual ground.
11. An integrated circuit, comprising:
logic circuitry coupled to a virtual ground;
a ground constriction circuit coupled between the virtual ground and a ground reference, the ground constriction circuit including a first transistor sourcedrain coupled between the virtual ground and ground reference and having a gate terminal coupled to receive a first control signal that changes an amount of current sourced by the first transistor; and
a tracking circuit comprised of same logic circuitry and operable to track leakage current of that same logic circuitry and generate the first control signal to change the amount of current sourced by the first transistor so as to maintain a substantially steady voltage across the logic circuitry.
12. The integrated circuit of claim 9 wherein the logic circuitry is coupled between the virtual ground and a virtual supply, further comprising a supply constriction circuit coupled between the virtual supply and a supply reference, the supply constriction circuit including a second transistor sourcedrain coupled between the virtual supply and supply reference and having a gate terminal coupled to receive a second control signal that changes an amount of current sourced by the second transistor.
13. An integrated circuit, comprising:
logic circuitry coupled between a virtual ground and a virtual supply;
a ground constriction circuit coupled between the virtual ground and a ground reference, the ground constriction circuit including a first transistor sourcedrain coupled between the virtual ground and ground reference and having a gate terminal coupled to receive a first control signal that changes an amount of current sourced by the first transistor;
a supply constriction circuit coupled between the virtual supply and a supply reference, the supply constriction circuit including a second transistor sourcedrain coupled between the virtual supply and supply reference and having a gate terminal coupled to receive a second control signal that changes an amount of current sourced by the second transistor; and
a tracking circuit comprised of same logic circuitry and operable to track leakage current of that same logic circuitry and generate the first and second control signals to change the amount of current sourced by the first and second transistors so as to maintain a substantially steady voltage across the logic circuitry.