1. A computer based method for providing a human user with a guided movement and feedback, the method comprising:
providing to the user an instruction to perform the guided movement;
capturing a movement performed by the user in response to the instruction;
estimating a movement of the user in a human model based on the captured movement performed by the user;
determining a biomechanical quantity of the user by analyzing the estimated movement in the human model; and
providing feedback to the user about the captured movement performed by the user based on the biomechanical quantity.
2. The method of claim 1, wherein capturing the movement comprises capturing the movement in a depth image stream using a depth camera, and wherein estimating the movement of the user comprises:
detecting features in the depth image stream and representing the detected features by position vectors;
filtering the position vectors to generate interpolated position vectors;
augmenting the interpolated position vectors with positions of features missing in the depth image stream; and
generating an estimated movement of the user based on the augmented position vectors.
3. The method of claim 2, wherein the features are detected by comparing Inner Distance Shape Context (IDSC) descriptors of sample contour points with IDSC descriptors of known feature points for similarity.
4. The method of claim 3, wherein the feature point comprises one of: head top, left shoulder, right shoulder, left elbow, right elbow, left wrist, right wrist, left waist, right waist, groin, left knee, right knee, left ankle, and right ankle
5. The method of claim 1, wherein the human model is a human anatomical model that closely resembles the body of the user.
6. The method of claim 5, wherein the human model is configured based on a plurality of appropriate kinematic model parameters and appropriate dynamic model parameters of a plurality of body parts of the user.
7. The method of claim 6, wherein one or more of the plurality of appropriate kinematic model parameters are obtained from images of the user.
8. The method of claim 1, wherein the biomechanical quantity comprises a center of pressure (COP) and the COP is determined using a Recursive Newton-Euler Algorithm (RNEA).
9. The method of claim 1, wherein the biomechanical quantity comprises a muscle force, and the muscle force is determined by modeling muscle and tendon mechanics as active force-generating elements in series and parallel with elastic elements.
10. The method of claim 9, wherein the muscle force is determined using a generic musculo-tendon model that is scaled to individual muscles using the following muscle specific parameters: a maximum isometric force capacity of muscle, an optimal muscle fiber length, a muscle fiber pennation angle at optimal fiber length, and a tendon slack length.
11. The method of claim 9, wherein determining the muscle force comprises iteratively updating the fiber length and recomputing a percentage force error until the percentage force error is less than a predetermined value.
12. The method of claim 1, wherein providing the feedback comprises:
displaying a human model tracking the estimated movement of the user along with the guided movement.
13. The method of claim 11, wherein providing the feedback further comprises:
amplifying the differences between the estimated movement and the guided movement.
14. The method of claim 1, further comprising:
transmitting the biomechanical quantity to a human expert, wherein the feedback comprises feedback provided by the human expert in response to the biomechanical quantity.
15. The method of claim 1, wherein the instruction to perform the guided movement comprises one of a voice command and a motion command graphically displayed to the user by means of the human model.
16. The method of claim 1, wherein the feedback comprises a physical robot that replicates the subject’s movements.
17. The method of claim 16, wherein the physical robot is further configured to provide at least one of the following: physical interaction, physical assistance, and resistive training
18. The method of claim 1, wherein the guided movement comprises one of the following: mirror therapy, balance & stability based on regulation of the center of pressure (COP) and the center of gravity (COG), balance & stability based on pose regulation, motion sequence recall, voice and posture, posture and hand shape, and listening to words and gesture.
19. A computer program product for providing a human user with a guided movement and feedback, the computer program product comprising a computer-readable storage medium containing executable computer program code for performing a method comprising:
providing to the user an instruction to perform the guided movement;
capturing a movement performed by the user in response to the instruction;
estimating a movement of the user in a human model based on the captured movement performed by the user;
determining a biomechanical quantity of the user by analyzing the estimated movement in the human model; and
providing feedback to the user about the captured movement performed by the user based on the biomechanical quantity.
20. A system for providing a human user with a guided movement and feedback, the system comprising:
a computer processor for executing executable computer program code;
a computer-readable storage medium containing the executable computer program code for performing a method comprising:
providing to the user an instruction to perform the guided movement;
capturing a movement performed by the user in response to the instruction;
estimating a movement of the user in a human model based on the captured movement performed by the user;
determining a biomechanical quantity of the user by analyzing the estimated movement in the human model; and
providing feedback to the user about the captured movement performed by the user based on the biomechanical quantity.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A 4T2R cell for a non-volatile ternary content-addressable memory, the 4T2R cell comprising:
a write transistor, controlled by a write-line, the drain electrode of the write transistor electrically coupled to a bias voltage;
a first variable resistive element, electrically coupled to the source of the write transistor;
a first transistor, electrically coupled to the first variable resistive element in series, controlled by a first search-line;
a second variable resistive element, electrically coupled to the source of the write transistor;
a second transistor, electrically coupled to the second variable resistive element in series, controlled by a second search-line, the source electrode of the second transistor and the source electrode of the first transistor being connected together; and
a charge control transistor, electrically coupling to a match-line for controlling the voltage level of the match-line, the gate electrode of the charge control transistor electrically coupled to the source of the write transistor, the first variable resistive element and the second variable resistive element;
wherein when the 4T2R cell operates in a search phase, a pulse voltage is applied across the gate electrode and the source electrode of the first transistor for determining whether the gate voltage of the charge control transistor changes larger than a match threshold during the period of the pulse, and the pulse voltage is applied across the gate electrode and the source electrode of the second transistor for determining whether the gate voltage of the charge control transistor changes larger than the match threshold during the period of the pulse.
2. The 4T2R cell according to claim 1, wherein the difference between the match threshold and a voltage applied to the source electrode of the charge control transistor is the threshold voltage of the charge control transistor.
3. The 4T2R cell according to claim 1, wherein the variation of the gate voltage of the charge control transistor is due to RC time constant of a RC circuit constituted of the first variable resistive element and the parasitic capacitor of the first variable resistive element, and is due to RC time constant of a RC circuit constituted of the second variable resistive element and the parasitic capacitor of the second variable resistive element.
4. The 4T2R cell according to claim 1, wherein when the pulse voltage is inputted to the source electrodes of the first transistor and the second transistor, the voltage difference between the gate electrode and the source electrode of the first transistor is increased to be larger than the threshold voltage of the first transistor, the voltage difference between the gate electrode and the source electrode of the second transistor is increased to be larger than the threshold voltage of the second transistor.
5. The 4T2R cell according to claim 1, wherein the pulse voltage is inputted to the gate electrode of the first transistor or the gate electrode of the second transistor for turning on the first transistor or the second transistor respectively, a constant voltage is applied to the source electrodes of the first transistor and the second transistor.
6. The 4T2R cell according to claim 1, wherein the first variable resistive element and the second variable resistive element are utilized as the phase change random-access memory (PCRAM), the resistive random-access memory (RRAM) or the magnetoresistive random-access memory (MRAM).
7. The 4T2R cell according to claim 6, wherein a logic \u201c0\u201d, a logic \u201c1\u201d or a logic \u201cX\u201d (don’t care) is stored in the 4T2R cell.
8. The 4T2R cell according to claim 7, wherein the first variable resistive element and the second variable resistive element both have a high resistance state and a low resistance state.
9. The 4T2R cell according to claim 8, the logic \u201c1\u201d is stored in the 4T2R cell when the first variable resistive element is at the high resistance state and the second variable resistive element is at the low resistance state, the logic \u201c0\u201d is stored in the 4T2R cell when the first variable resistive element is at the low resistance state and the second variable resistive element is at the high resistance state, the logic \u201cX\u201d is stored in the 4T2R cell when the first variable resistive element and the second variable resistive element are both at the high resistance state.
10. The 4T2R cell according to claim 9, wherein on condition that the logic \u201c1\u201d is stored in the 4T2R cell, the gate voltage of the charge control transistor is changed to be less than the match threshold during the pulse period due to RC-delay when the first search-line is at a high logic state and the second search-line is at a low logic state, the gate voltage of the charge control transistor is changed to be larger than the match threshold during the pulse period due to RC-delay when the first search-line is at the low logic state and the second search-line is at the high logic state.
11. The 4T2R cell according to claim 9, wherein on condition that the logic \u201c0\u201d is stored in the 4T2R cell, the gate voltage of the charge control transistor is changed to be larger than the match threshold during the pulse period due to RC-delay when the first search-line is at a high logic state and the second search-line is at a low logic state, the gate voltage of the charge control transistor is changed to be less than the match threshold during the pulse period due to RC-delay when the first search-line is at the low logic state and the second search-line is at the high logic state.
12. The 4T2R cell according to claim 9, wherein on condition that the logic \u201cX\u201d is stored in the 4T2R cell, the gate voltage of the charge control transistor is changed to be less than the match threshold during the pulse period due to RC-delay when the first search-line is at a high logic state and the second search-line is at a low logic state, the gate voltage of the charge control transistor is changed to be less than the match threshold during the pulse period due to RC-delay when the first search-line is at the low logic state and the second search-line is at the high logic state.
13. The 4T2R cell according to claim 1, wherein the write transistor, the first transistor, the second transistor, and the charge control transistor are N-channel MOSFETs.
14. A non-volatile ternary content-addressable memory comprising a plurality of 4T2R cells, each 4T2R cell comprising:
a write transistor, controlled by a write-line, the drain electrode of the write transistor electrically coupled to a bias voltage;
a first variable resistive element, electrically coupled to the source of the write transistor;
a first transistor, electrically coupled to the first variable resistive element in series, controlled by a first search-line;
a second variable resistive element, electrically coupled to the source of the write transistor;
a second transistor, electrically coupled to the second variable resistive element in series, controlled by a second search-line, the source electrode of the second transistor and the source electrode of the first transistor being connected together; and
a charge control transistor, electrically coupling to a match-line for controlling the voltage level of the match-line, the gate electrode of the charge control transistor electrically coupled to the source of the write transistor, the first variable resistive element and the second variable resistive element;
wherein when the 4T2R cell operates in a search phase, a pulse voltage is applied across the gate electrode and the source electrode of the first transistor for determining whether the gate voltage of the charge control transistor changes larger than a match threshold during the period of the pulse, and the pulse voltage is applied across the gate electrode and the source electrode of the second transistor for determining whether the gate voltage of the charge control transistor changes larger than the match threshold during the period of the pulse.
15. The non-volatile ternary content-addressable memory according to claim 14, wherein the difference between the match threshold and a voltage applied to the source electrode of the charge control transistor is the threshold voltage of the charge control transistor.
16. The non-volatile ternary content-addressable memory according to claim 14, wherein the variation of the gate voltage of the charge control transistor is due to RC time constant of a RC circuit constituted of the first variable resistive element and the parasitic capacitor of the first variable resistive element, and is due to RC time constant of a RC circuit constituted of the second variable resistive element and the parasitic capacitor of the second variable resistive element.
17. The non-volatile ternary content-addressable memory according to claim 14, wherein when the pulse voltage is inputted to the source electrodes of the first transistor and the second transistor, the voltage difference between the gate electrode and the source electrode of the first transistor is increased to be larger than the threshold voltage of the first transistor, the voltage difference between the gate electrode and the source electrode of the second transistor is increased to be larger than the threshold voltage of the second transistor.
18. The non-volatile ternary content-addressable memory according to claim 14, wherein the pulse voltage is inputted to the gate electrode of the first transistor or the gate electrode of the second transistor to turn on the first transistor or the second transistor respectively, a constant voltage is applied to the source electrodes of the first transistor and the second transistor.
19. The non-volatile ternary content-addressable memory according to claim 14, wherein a logic \u201c0\u201d, a logic \u201c1\u201d or a logic \u201cX\u201d (don’t care) is stored in the 4T2R cell, the first variable resistive element and the second variable resistive element both have a high resistance state and a low resistance state.
20. The non-volatile ternary content-addressable memory according to claim 14, wherein the write transistor, the first transistor, the second transistor, and the charge control transistor are N-channel MOSFETs.