1. A controller for a hybrid electric vehicle (HEV), the controller configured to determine a value of driver demanded torque to be supplied to a driveline of a vehicle by a first and at least a second actuator of the vehicle based on a plurality of parameters, the plurality of parameters including:
(a) a speed of a first actuator; and
(b) a position of a driver-operated accelerator control, the controller being configured such that when the first actuator is not connected to the driveline a value of driver demanded torque is determined based on a virtual speed of the first actuator and the position of the driver-operated accelerator control, the virtual speed of the first actuator being a speed at which the first actuator would be turning if the first actuator was connected to the driveline.
2. A controller as claimed in claim 1 arranged to determine the virtual speed of a first actuator based on one selected from amongst a measured speed of a second actuator and a calculated speed of a second actuator, the calculated speed being calculated based on a currently demanded speed of a second actuator.
3. A controller as claimed in claim 1 arranged to determine the virtual speed of the first actuator taking into account a gear ratio between the first actuator and the second actuator that would be experienced by the first actuator if the first actuator were connected to the driveline.
4. A controller as claimed in claim 1 arranged to determine the virtual speed of the first actuator based on one selected from amongst a speed of the driveline at a speed measurement position of the driveline, a wheel speed, and a gear ratio between the first actuator and the speed measurement position of the driveline.
5. A controller as claimed in claim 1 operable when the first actuator is not connected to the driveline to estimate an amount of braking torque that would be provided to the driveline by the first actuator if the first actuator were connected to the driveline in dependence on at least the virtual speed of the first actuator, the controller being further operable to control the at least a second actuator to deliver an amount of torque to the driveline corresponding to a net torque that would be delivered if the first actuator were connected to the driveline.
6. A controller as claimed in claim 5 operable to estimate the amount of braking torque that would be further provided in further dependence on at least one selected from amongst the position of the driver-operated accelerator control, the speed of the vehicle and a gear ratio between a wheel of the vehicle and the first actuator.
7. A controller as claimed in claim 1 operable when the first actuator is not connected to the driveline to determine a maximum amount of torque that would be available from the first actuator if the first actuator was connected to the driveline in dependence on the virtual speed of the first actuator.
8. A controller as claimed in claim 7 operable to determine whether or not it is required to start the first actuator in dependence on the position of the driver-operated accelerator control and the maximum amount of torque that would be available from the first actuator if the first actuator were connected to the driveline.
9. A hybrid electric vehicle (HEV) comprising a controller as claimed in claim 1.
10. A vehicle as claimed in claim 9 wherein the first actuator comprises an internal combustion engine and the second actuator comprises an electric machine.
11. A controller as claimed in claim 10 wherein the electric machine comprises an electric motorgenerator arranged to be operated as a motor or as a generator, the second actuator optionally comprising a crankshaft-integrated motorgenerator (CIMG).
12. A vehicle as claimed in claim 9 wherein the first actuator is arranged to be coupled to the driveline via the second actuator.
13. A vehicle as claimed in claim 9 wherein the second actuator is comprised in a rear axle drive (RAD) unit.
14. A vehicle as claimed in claim 13 wherein the RAD unit is provided between a gearbox or transmission of the driveline and at least one wheel of the vehicle driven by the RAD unit.
15. A method of controlling a hybrid electric vehicle (HEV) comprising the step of determining a value of driver demanded torque to be supplied to a driveline of the vehicle by first and second actuators of the vehicle based on a plurality of parameters, the parameters including:
(a) a speed of a first actuator; and
(b) a position of a driver-operated control,
when the first actuator is not connected to the driveline the method comprising determining a value of driver demanded torque based on a virtual speed of the first actuator and the position of the driver-operated control, the virtual speed of the first actuator being a speed at which the first actuator would be turning if the first actuator was connected to the driveline.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for dynamically allocates memories in an Ethernet Switching architecture, comprising steps of:
Providing a plurality of input ports and output ports for respectively receiving and transmitting packet segments of a plurality of packets;
Providing a dynamic random access memory as a shared memory to store the packet segments after been received from the plurality of input ports but before transmitted out from the plurality of output ports;
Providing a first link RAM mapping to the shared memory for controlling a making of a single linked list for the packet segments of each of the plurality of packets while writing the plurality of packets onto the shared memory, and for controlling a reading of the single linked list while reading the plurality of packets; and
Providing a second link RAM serving as a first in first out device for co-managing an obtaining of the link address spaces at the corresponding input port before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.
2. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 1, wherein the second link RAM is configured to have an address width no larger than that of the first link RAM.
3. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 1, wherein the shared memory is configured to have a plurality of blocking data buffers with same size, and the first link RAM and the second link RAM are configured respectively to have a plurality of link address spaces that are the same as the plurality of blocking data buffers in number.
4. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 3, wherein the size of the plurality of blocking data buffers is 256 bytes.
5. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 3, wherein one packet of the plurality of packets can fill a maximum of six blocks on the shared memory.
6. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 3, wherein for co-managing an obtaining of the link address spaces at the corresponding input port before the single linked list been made is to request the second link RAM for a free-link address spaces when the link address space counts is less than a fixed count;
Wherein the fixed count is substantially the quotient of a maximum length of a packet to the size of the blocking data buffers; and
Wherein the free-link address space is corresponding to a usable link address space of the first link RAM.
7. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 6, wherein the fixed count is 6.
8. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 3, wherein for controlling a making of a single linked list for the packet segments of each of the plurality of packets while writing the plurality of packets onto the shared memory comprising steps of:
To write in a packet data, comprising steps of:
To request the shared memory for at least one blank block;
Start to write with the first block requested on the shared memory;
Write in data of the packet segments according to the packet size, the link addresses for the packet segments of the packet on the first link RAM, and the mapping block addresses for the packet segments on the shared memory; and
Write the entire mapping block addresses of the packet segments onto the shared memory in a single process; and
Making links when the packet is not the first packet for the designated output port, writing in the flag of the packet and inform the output port the starting link address for the packet segments of the packet on the first link RAM when the packet is the first packet for the designated output port.
9. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 8, wherein making links is to insert the single linked list of the packet segments to the tail address of the output port.
10. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 3, wherein for co-managing a releasing of the link address spaces at the corresponding output ports after the single linked list been read is to insert the link address spaces which have been completely read on the first link RAM to the tail address on the second link RAM in a manner of first in first out order through the second link RAM.
11. The method for dynamically allocates memories in an Ethernet Switching architecture according to claim 3, wherein for controlling a reading of the single linked list while reading the plurality of packets comprises steps of:
To read a header address of an output queue of the corresponding output port for getting the link address of a first packet segment of a packet;
To read the entire block addresses of the packet segments of the packet on the shared memory in a single process and simultaneously judge whether there is a next packet waiting for transmission;
To read the packet data according to the current link addresses for the packet segments of the packet on the first link RAM, and the block addresses on the shared memory;
To read the single linked list and linked list address table on the first link RAM for the entire packet segments when there exists a next packet waiting for transmission, so as to insert the next packet waiting for transmission to the header address of the output queue; and
Proceed to read the next packet waiting for transmission when either the packet has been completely read or abortively transmit.
12. An Ethernet switching architecture, comprising:
A plurality of input ports for receiving packet segments of a plurality of packets;
A plurality of output ports for transmitting the packet segments;
A shared memory being a dynamic random access memory for storing the packet segments after been received from the plurality of input ports but before transmitted out from the plurality of output ports;
A first link RAM mapping to the shared memory for controlling a making of a single linked list for the packet segments of each the plurality of packets while writing the plurality of packets onto the shared memory, and for controlling a reading of the single linked list while reading the plurality of packets; and
A second link RAM serving as a first in first out device for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.
13. The Ethernet switching architecture according to claim 12, wherein the second link RAM have an address width no larger than that of the first link RAM.
14. The Ethernet switching architecture according to claim 12, wherein the shared memory have a plurality of blocking data buffers with same size, and the first link RAM and the second link RAM are configured respectively to have a plurality of link address spaces that are the same as the plurality of blocking data buffers in number.
15. The Ethernet switching architecture according to claim 14, wherein the plurality of blocking data buffers have a size of 256 bytes.
16. The Ethernet switching architecture according to claim 14, wherein the shared memory can be filled with the packet segments of a packet of the plurality of packets on a maximum of six blocks.
17. The Ethernet switching architecture according to claim 14, wherein the plurality of blocking data buffers on the shared memory comprises:
A plurality of blank blocks in a free-buffer pool; and
A plurality of blocks in the plurality of assigned buffers for writing.
18. The Ethernet switching architecture according to claim 17, wherein the plurality of blocks in the plurality of assigned buffers for writing comprises:
Blank blocks to be assigned to the packet segments waiting to be received; and
Blank blocks released after the plurality of blocks of the plurality of assigned buffers for writing have been completely read.
19. The Ethernet switching architecture according to claim 17, wherein the plurality of blank blocks in the free-buffer pool are corresponding to the plurality of link address spaces on the second link RAM.
20. The Ethernet switching architecture according to claim 12, wherein for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made is to request the second link RAM for at least one free-link address space when the link address spaces counts is less than a fixed count;
Wherein the free-link address space is corresponding to a usable link address space of the first link RAM.
21. The Ethernet switching architecture according to claim 20, wherein the fixed count is 6.
22. The Ethernet switching architecture according to claim 12, wherein for co-managing a releasing of the link address spaces at the corresponding output ports after the single linked list been read is to insert the link address spaces which have been completely read on the first link RAM to the tail address on the second link RAM in a manner of first in first out order through the second link RAM.
23. The Ethernet switching architecture according to claim 12, wherein a packet of the plurality of packets has a maximum length of 1536 bytes.
24. The Ethernet switching architecture according to claim 12, wherein the shared memory is a SRAM or DRAM.
25. The Ethernet switching architecture according to claim 12, wherein the first link RAM is a SRAM or DRAM.
26. The Ethernet switching architecture according to claim 12, wherein the second link RAM is a SRAM or DRAM.