1. An ink cartridge, comprising:
a body, having a plurality of ink chambers for storing ink, the body having a first sidewall, a second sidewall opposite to the first sidewall, a third sidewall, a fourth sidewall opposite to the third sidewall, and a bottom;
a channel module, attached to the bottom of the body;
a plurality of first engaging parts, comprising a first pair of first engaging parts, the first pair of first engaging parts being respectively arranged at the two corners of the external surface of the bottom of the body and adjacent to the first sidewall; and
a plurality of second engaging parts, comprising a first pair of second engaging parts, the first pair of second engaging parts being respectively arranged at two corners of the channel module and corresponding to the first pair of first engaging parts, wherein the relative position of the body and the channel module on a two-dimension plane is substantially fixed by the engagement of the first engaging parts and the second engaging parts,
the first engaging parts further comprise a second pair of first engaging parts, and the second pair of first engaging parts are arranged on the external surface of the bottom of the body and are arranged in a way substantially parallel to and away from the first sidewall, and
the second engaging parts further comprise a second pair of second engaging parts, and the second pair of second engaging parts are arranged on the channel module and are respectively arranged corresponding to the second pair of first engaging parts so as to respectively engage with the second pair of first engaging parts.
2. The ink cartridge as claimed in claim 1, wherein one of the first engaging parts and the corresponding one of the second engaging parts are a block and an indentation.
3. The ink cartridge as claimed in claim 1, wherein the bottom of the body has a plurality of ink delivery ports respectively fluidly communicating with the ink chambers; the channel module has a chip bonding area, a plurality of ink supply ports, and a plurality of flow channels; and the ink supply ports are located in the chip bonding area, and the flow channels respectively fluidly communicate the ink delivery ports with the ink supply ports.
4. The ink cartridge as claimed in claim 3, wherein a section of at least one flow channel of the flow channels which is substantially parallel to the two-dimension plane extends from the chip bonding area to an area outside the chip bonding area.
5. The ink cartridge as claimed in claim 4, wherein the ink supply ports are arranged in sequence, and the extending direction of the section is substantially parallel to the arrangement direction of the ink supply ports.
6. The ink cartridge as claimed in claim 4, wherein the ink chambers are arranged in sequence, and the extending direction of the section is substantially parallel to the arrangement direction of the ink chambers.
7. The ink cartridge as claimed in claim 3, wherein the ink chambers are arranged in sequence, the ink supply ports are arranged in sequence, and the arrangement direction of the ink chambers is substantially parallel to the arrangement direction of the ink supply ports.
8. The ink cartridge as claimed in claim 1, wherein the channel module has a base attached to the body, an uplift portion protruding from the base, and a chip bonding area located on the uplift portion; the base has a base surface, the uplift portion protrudes from the base surface and has a side surface connecting the base surface and the chip bonding area, and the angle between the side surface and the base surface is between 90 degrees and 135 degrees.
9. The ink cartridge as claimed in claim 1, wherein the channel module has a first edge, a second edge opposite to the first edge, a third edge, and a four edge opposite to the third edge, the first pair of second engaging parts are arranged at the first edge, and the second pair of second engaging parts are arranged at the second edge.
10. The ink cartridge as claimed in claim 1, wherein the second pair of first engaging parts are respectively arranged at the another two corners of the external surface of the bottom of the body and adjacent to the second sidewall; and
the second pair of second engaging parts are respectively arranged corresponding to the second pair of first engaging parts and at another two corners of the channel module to respectively engage with the second pair of first engaging parts.
11. An ink cartridge, comprising:
a body, having a plurality of ink chambers for storing ink, the body having a first sidewall, a second sidewall opposite to the first sidewall, a third sidewall, a fourth sidewall opposite to the third sidewall, and a bottom;
a channel module, attached to the bottom of the body;
a plurality of first engaging parts, comprising a first pair of first engaging parts, the first pair of first engaging parts being respectively arranged at the two corners of the external surface of the bottom of the body and adjacent to the first sidewall;
a plurality of second engaging parts, comprising a first pair of second engaging parts, the first pair of second engaging parts being respectively arranged at two corners of the channel module and corresponding to the first pair of first engaging parts, wherein the relative position of the body and the channel module on a two-dimension plane is substantially fixed by the engagement of the first engaging parts and the second engaging parts;
a block, protruding from the external surface of the bottom and being arranged adjacent to the second sidewall, the block being extended parallel to the first sidewall; and a recess, formed on an edge of the channel module and being arranged in a way corresponding to the block so as to engage with the block.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A multi-layer electronic device package comprising:
first and second outer layers; and
a plurality of signal layers disposed between the outer layers, the signal layers including signal traces and ground traces interleaved with the signal traces.
2. The multi-layer electronic device package of claim 1 wherein the first outer layer defines a ground layer.
3. The multi-layer electronic device package of claim 1 wherein the second outer layer defines a power source layer.
4. The multi-layer electronic device package of claim 1 wherein the plurality of signal layers comprises three signal layers.
5. The multi-layer electronic device package of claim 1 wherein the ground traces are interleaved with signal traces within the signal layer.
6. The multi-layer electronic device package of claim 1 wherein the ground traces are interleaved with signal traces between signal layers.
7. The multi-layer electronic device package of claim 1 wherein the outer layers and the signal layers define a plurality of vias.
8. The multi-layer electronic device package of claim 1 wherein the signal traces are configured to route at least 250 signals.
9. The multi-layer electronic device package of claim 1 wherein the signal traces are adapted to interconnect a processor and a memory device.
10. The multi-layer electronic device package of claim 9 further comprising a processor and a memory device coupled to the multi-layer electronic device package such that the signal traces interconnect the processor and the memory device.
11. A multi-layer electronic device package comprising:
a ground layer;
a power layer;
a plurality of signal layers, each signal layer including a plurality of signal traces; and
means for shielding the signal traces from each other.
12. A method of routing signal traces in an electronic device package comprising the acts of:
disposing a plurality of signal traces in at least one substrate layer; and
interleaving a plurality of ground traces with the signal traces.
13. The method, of claim 12 wherein the disposing act further comprises disposing the signal traces in at least one substrate layer situated between a ground layer and a power layer.
14. The method of claim 12 wherein the disposing act further comprises disposing the signal traces in three substrate layers.
15. The method of claim 12 wherein the interleaving act comprises interleaving the ground traces with the signal traces within at least one of the substrate layers.
16. The method of claim 12 wherein the interleaving act comprises interleaving the ground traces with the signal traces between the substrate layers.
17. The method of claim 12 wherein the disposing the signal traces act further comprises disposing the signal traces so as to route at least 250 signals.
18. The method of claim 12 wherein the disposing the signal traces act further comprises coupling the signal traces between a processor and a memory device.
19. A semiconductor device comprising:
a first semiconductor die;
a second semiconductor die; and
a multi-layer package, the first die and the second die being mounted on the multi-layer package;
the multi-layer package defining at least one signal layer, each signal layer including signal traces and ground traces interleaved therewith, the signal traces interconnecting the first die and the second die.
20. The semiconductor device of claim 19 wherein the first semiconductor die is disposed in a first component package that is mounted on the multi-layer package.
21. The semiconductor device of claim 20 wherein the second semiconductor die is disposed in a second component package that is mounted on the multi-layer package.
22. The semiconductor device of claim 19 wherein the at least one signal layer comprises three signal layers.
23. The semiconductor device of claim 19 wherein the first semiconductor die comprises a processor.
24. The semiconductor device of claim 19 wherein the second semiconductor die comprises at least one memory device.
25. The semiconductor device of claim 24 wherein the at least one memory device comprises two memory devices.
26. The semiconductor device of claim 25 wherein the memory devices are situated on opposite sides of the processor.
27. The semiconductor device of claim 25 wherein the memory devices are situated on one side of the processor.
28. The semiconductor device of claim 19 wherein the ground traces are interleaved with the signal traces within at least one of the signal layers.
29. The semiconductor device of claim 19 wherein the ground traces are interleaved with the signal traces between signal layers.
30. The semiconductor device of claim 19 further comprising a plurality of vias that couple the signal traces to the first semiconductor die and the second semiconductor die.
31. A multi-layer electronic device package comprising:
a plurality of signal traces; and
a plurality of ground traces interleaved with the plurality of signal traces.
32. The multi-layer electronic device package of claim 31 wherein the signal traces and the ground traces are incorporated in at least one substrate layer.
33. The multi-layer electronic device package of claim 32 wherein the ground traces are interleaved with the signal traces within at least one substrate layer.
34. The multi-layer electronic device package of claim 32 wherein the ground traces are interleaved with the signal traces between substrate layers.