1. A Dynamic Random Access Memory (DRAM) having a memory core having a plurality of addressable memory elements, said memory comprising;
a data path having one or more pipelined stages defined between an address input port and an IO data port, said one or more pipelined stages latching data from said IO port in response to a corresponding asynchronous control signal from a plurality of asynchronous control signals; and
a plurality of delay elements for generating said plurality of asynchronous control signals, from a system clock signal and a master control signal, said asynchronous control signals being independent from said system clock signal; and
a synchronization circuit coupled to said IO port for synchronizing output data read from said memory core to said system clock signal.
2. The Dynamic Random Access Memory as claimed in claim 1, wherein the data path comprises a read path for reading an addressed memory element in the memory core.
3. The Dynamic Random Access Memory as claimed in claim 1, wherein the data path comprises an address input port for receiving an address corresponding to a memory element to be accessed.
4. The Dynamic Random Access Memory as claimed in claim 3, wherein the address is clocked into the address input port on a system clock signal.
5. The Dynamic Random Access Memory as claimed in claim 1, wherein the data path comprises a data output port for providing output data.
6. The Dynamic Random Access Memory as claimed in claim 5, further comprising a synchronization circuit for providing the output data to the data output port in response to a system clock signal.
7. The Dynamic Random Access Memory as claimed in claim 6, wherein the synchronization circuit includes a plurality of output latches coupled in parallel to receive data from the memory core, each of the output latches being responsive to respective latch enable signals for latching the data from the memory core into a selected one of the plurality of output latches.
8. The Dynamic Random Access Memory as claimed in claim 7, wherein the synchronization circuit further comprises a counter for generating the latch enable signals.
9. The Dynamic Random Access Memory as claimed in claim 8, wherein the counter is clocked by the system clock signal.
10. The Dynamic Random Access Memory as claimed in claim 8, wherein the counter has a reset input for resetting the counter in accordance with the number of pipelined stages in the memory.
11. The Dynamic Random Access Memory as claimed in claim 6, wherein the synchronization circuit includes an output latch coupled to receive data from the memory core, the output latch being responsive to a latch enable signal for latching the data from the memory core into the output latch.
12. The Dynamic Random Access Memory as claimed in claim 5, further comprising a synchronization circuit for providing the output data to the data output port in synchronization with an edge of a system clock signal.
13. The Dynamic Random Access Memory as claimed in claim 1, wherein the data path includes a first group of pipelined stages and a second group of pipelined stages for implementing a double data rate (DDR) memory access mode.
14. The Dynamic Random Access Memory as claimed in claim 13, wherein the first and second groups of pipelined stages each comprise a plurality of pipeline stages.
15. The Dynamic Random Access Memory as claimed in claim 14, further comprising an edge detector for detecting rising and falling edges of the system clock signal, and means for directing output of the memory core to the first or second group of pipelined stages, in accordance with the rising and falling edges of said system clock signal.
16. The Dynamic Random Access Memory as claimed in claim 15, wherein an address is clocked through the first and second groups of pipeline stages on the rising and falling edges of the system clock signal, respectively.
17. The Dynamic Random Access Memory as claimed in claim 13, wherein the first and second groups of pipelined stages each comprise at least three stages.
18. The Dynamic Random Access Memory as claimed in claim 1, wherein each delay element has a delay that is selected to accommodate a propagation delay of the corresponding pipelined stage.
19. The Dynamic Random Access Memory as claimed in claim 1, wherein the delay element comprises a circuit for generating data access control signals, the circuit for generating data access control signals having a first time delay.
20. The Dynamic Random Access Memory as claimed in claim 19, wherein the circuit for generating data access control signals further comprises an additional timing delay element for adding a second time delay to first time delay.
21. The Dynamic Random Access Memory as claimed in claim 20, wherein the timing delay element comprises a capacitive circuit element.
22. A method for pipelining access to a Dynamic Random Access Memory (DRAM), the DRAM memory comprising a memory core having a plurality of addressable memory elements and a data path for accessing the memory elements, comprising:
segmenting the data path into a plurality of pipelined stages, each pipelined stage being adapted to be controlled by a respective asynchronous control signal;
generating the asynchronous control signals for controlling the pipelined stages by delaying each control signal to accommodate propagation delays of each pipeline stage; and
resynchronizing a last pipelined stage of the data path with a system clock.
23. A method for pipelining access to a Dynamic Random Access Memory (DRAM), the DRAM memory comprising a memory core having a plurality of addressable memory elements and a data path for accessing the memory elements, the data access path comprising a plurality of pipelined stages, each stage having an associated latency time, the method comprising:
initiating a memory access cycle in synchronism with a system clock;
generating an asynchronous control signal for controlling each pipelined stage, the asynchronous control signal being time delayed relative to the initiation of the memory access cycle by the latency time for the pipelined stage; and
providing a last pipelined stage in the data path with an output data port for outputting data in alignment with the system clock.
24. The method as claimed in claim 23, wherein delaying each control signal comprises inserting delay elements between the asynchronous control signals.
25. The method as claimed in claim 23, wherein segmenting further comprises providing a first pipelined stage that receives an address signal on a rising edge of the system clock.
26. The method as claimed in claim 23, wherein segmenting further comprises providing top and bottom first pipelined stages that receive address signals on a rising edge of the system clock, and a falling edge of the system clock, respectively.
27. The method as claimed in claim 23, wherein segmenting further comprises providing a first pipelined stage that receives an address signal a falling edge of the system clock.
28. A pipelined synchronous dynamic random access memory comprising:
an address input port (25);
a memory core (22) having addressable memory elements;
an IO data output port (32);
a read data path (24) defined between said address input port (25) and said IO data output port (32), said read path (24) including a plurality of pipeline stages (27), each pipeline stage (27) including latches responsive to a corresponding asynchronous control signal (23); and
a delay element (T1, T2, T3) associated with each pipeline stage (27) for generating said corresponding asynchronous control signals (23) as delayed versions of a system clock (CLK),
characterized in that a first delay element (T1) is arranged to generate the control signal (23) based on the system clock (CLK), subsequent delay elements in the pipeline are arranged to generate the control signals (23) using the control signals (23) generated by a preceding delay element in the pipeline, and each of said delay elements (T1, T2, T3) has a latency corresponding to a latency of its associated pipeline stage (27), such that the pipeline stages (27) controlled by control signals (23) generated by subsequent delay elements are controlled asynchronously to said system clock (CLK).
29. A memory as defined in claim 28, including a synchronization circuit (30) coupled to said IO data output port (32) for synchronizing output data to said system clock (CLK).
30. A memory as defined in claim 29, wherein said synchronization circuit (30) includes a plurality of pipe latches (51) coupled in parallel, and each responsive to respective pipe control signals (LATCH_ENX) for sequentially inputting data into successive latches (56).
31. A memory as defined in claim 30, including a pipe counter (64) for generating said pipe control signals (LATCH_ENX), said pipe counter (64) including pipe delay elements (66) coupled to an output thereof.
32. A memory as defined in claim 29, said synchronization circuit (30) including:
a plurality of output latches (56) for latching said output data;
an output latch signal generator (68) for sequentially generating from said system clock (CLK):
i. a set of output latch input enable signals (LATCH_ENX), each having a predetermined delay with respect to said system clock (CLK); and
ii. a set of output latch output enable signals (QEN_RISEX), each having a delay in accordance with a column address select latency of said pipelined memory; and
a delay latch circuit (58) for coupling said output latch output enable signals (QEN_RISEX) to said output latches synchronous with said system clock.
33. A method for pipelining a synchronous dynamic random access memory; said method comprising the steps of:
defining a read path between an address input port (25) and an IO data port (32) of a memory core (22) having addressable memory elements, said path including one or more pipeline stages (27);
latching data from said IO data port (32) in response to a system clock (CLK);
generating asynchronous control signals (28) from a master control signal; and
controlling said pipeline stages (27) with said asynchronous control signals (28);
characterized in that each of said asynchronous control signals (28) is generated by delaying a control signal (28) received from a previous pipeline stage (27) in accordance with a latency of an associated one of said pipeline stages (27); and
said pipeline stages (27) are controlled using said asynchronous control signals (28) such that data latched in each of said pipeline stages (27) is timed asynchronously to said system clock (CLK).
34. A method as defined in claim 33, including the step of synchronizing output data to said system clock (CLK).
35. A method as defined in claim 34, wherein said step of synchronizing said output data to said system clock (CLK) includes the steps of:
(a) latching said output data in a plurality of output latches (56);
(b) sequentially generating from said system clock (CLK):
i. a set of output latch input enable signals (CNT_DEL), each having a predetermined delay with respect to said system clock (CLK); and
ii. a set of output latch output enable signals (QEN_RISEX), each having a delay in accordance with a column address select latency of said pipelined memory; and
(c) enabling said output latch output enable signals (QEN_RISEX) synchronous with said system clock (CLK).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
an active region formed on a semiconductor substrate;
an element isolation region formed on the semiconductor substrate so as to surround the active region; and
a gate electrode formed on the active region, wherein
a region that causes tensile stress so as to improve carrier mobility in the active region is provided in the element isolation region.
2. The semiconductor device according to claim 1, wherein a void is formed in the region that causes tensile stress.
3. The semiconductor device according to claim 1, wherein a material having a lower Young’s modulus than a Young’s modulus of a remaining portion of the element isolation region is provided in the region that causes tensile stress.
4. The semiconductor device according to claim 1, wherein a material having contractile characteristics is provided in the region that causes tensile stress.
5. The semiconductor device according to claim 1, wherein the active region is an N-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) region, and the region that causes tensile stress is provided in a portion of the element isolation region which is adjacent to the active region in a gate length direction.
6. The semiconductor device according to claim 5, further comprising another active region as a P-type MISFET region that is formed on the semiconductor substrate so as to be located next to the active region in the gate length direction and to be surrounded by the element isolation region, wherein the another active region has a gate length direction of <100> orientation.
7. The semiconductor device according to claim 5, further comprising another active region as a P-type MISFET region that is formed on the semiconductor substrate so as to be located next to the active region in a gate width direction and to be surrounded by the element isolation region, wherein the another active region has a gate length direction of <100> orientation.
8. The semiconductor device according to claim 1, wherein the active region is a P-type MISFET region, and the region that causes tensile stress is provided in a portion of the element isolation region which is adjacent to the active region in a gate width direction.
9. The semiconductor device according to claim 8, further comprising another active region as an N-type MISFET region that is formed on the semiconductor substrate so as to be located next to the active region in a gate length direction and to be surrounded by the element isolation region, wherein the another active region has a gate length direction of <110> orientation.
10. The semiconductor device according to claim 9, wherein a portion of the element isolation region which is located between the active region and the another active region is divided by a substrate region that extends in a gate width direction, and the region that causes tensile stress is provided also in one of the divided portions which is located adjacent to the another active region.
11. The semiconductor device according to claim 8, further comprising another active region as an N-type MISFET region that is formed on the semiconductor substrate so as to be located next to the active region in the gate width direction and to be surrounded by the element isolation region, wherein the another active region has a gate length direction of <110> orientation.
12. The semiconductor device according to claim 11, wherein the region that causes tensile stress is provided also in a portion of the element isolation region which is adjacent to the another active region in a gate length direction.
13. A method for manufacturing a semiconductor device including an active region formed on a semiconductor substrate, an element isolation region formed on the semiconductor substrate so as to surround the active region, and a gate electrode formed on the active region, comprising the steps of:
(a) forming a trench corresponding to the element isolation region; and
(b) forming an insulating film in the trench, wherein
in the step (a), a width or a sidewall taper angle of a prescribed portion of the trench is made smaller than a width or a sidewall taper angle of another portion of the trench.
14. The method according to claim 13, wherein, in the step (b), a void is formed in the prescribed portion of the trench by closing a top of the prescribed portion during formation of the insulating film.
15. The method according to claim 14, further comprising after the step (b) the step of (c) opening the void and providing in the opening a material having a lower Young’s modulus than a Young’s modulus of the insulating film or a material having contractile characteristics.
16. The method according to claim 15, further comprising after the step (c) the step of covering the material in the opening with another insulating film.
17. The method according to claim 13, wherein, in the step (b), by making a top part of the prescribed portion of the trench narrower than a top part of the another portion of the trench during formation of the insulating film, introduction of a deposition species into the prescribed portion is suppressed, whereby a material having a lower Young’s modulus than a Young’s modulus of the insulating film that is formed in the another portion is provided in the prescribed portion.
18. The method according to claim 13, further comprising after the step (b) the step of heat treating the insulating film formed in the trench.
19. The method according to claim 13, further comprising: between the steps (a) and (b) the step of oxidizing a side wall of the trench; and after the step (b) the step of planarizing a surface of the semiconductor substrate.
20. A method for manufacturing a semiconductor device including an active region formed on a semiconductor substrate, an element isolation region formed on the semiconductor substrate so as to surround the active region, and a gate electrode formed on the active region, comprising the steps of:
(a) forming a first trench corresponding to the element isolation region;
(b) forming an insulating film in the first trench;
(c) forming a second trench in the insulating film formed in a prescribed portion of the first trench; and
(d) closing at least a top of the second trench.
21. The method according to claim 20, wherein, in the step (d), a void is formed in the second trench by closing the top of the second trench.
22. The method according to claim 20, further comprising in the step (d) the step of (e) providing in the second trench a material having a lower Young’s modulus than a Young’s modulus of the insulating film or a material having contractile characteristics.
23. The method according to claim 22, further comprising after the step (e) the step of covering the material provided in the second trench with another insulating film.
24. The method according to claim 20, further comprising after the step (d) the step of heat treating the insulating film formed in the first trench.
25. The method according to claim 20, further comprising: between the steps (a) and (b), the step of oxidizing a side wall of the first trench; and after the step (d), the step of planarizing a surface of the semiconductor substrate.