1-11. (canceled)
12. A method of reporting a channel state for multiple input multiple output (MIMO) in a wireless local access network, the method comprising:
broadcasting, by an initiating station, a channel request frame including an initiator field and a recipient set field, the initiator field indicating an address of the initiating station, the recipient set field including a plurality of subfields indicating a plurality of recipients to prepare a channel response frame, each of the plurality of subfields including a recipient field indicating an identifier of each recipient, wherein the plurality of recipients receive independent data streams simultaneously over same channel bandwidth; and
sequentially receiving, by the initiating station, from each of the plurality of recipients, the channel response frame including the channel state for MIMO channel.
13. The method of claim 12, the method further comprising:
transmitting, by an initiating station, to the plurality of recipients, a null data packet frame to determine the channel state after broadcasting the channel request frame.
14. The method of claim 13, wherein a bandwidth of the channel response frame is equal to or narrower than a bandwidth of the null data packet frame.
15. The method of claim 13, wherein the channel request frame further includes a duration field indicating an estimated time required to transmit the null data packet frame and the channel response frame.
16. The method of claim 15, wherein the channel request frame further includes a receiver address field which is set to a broadcast address.
17. A wireless apparatus of reporting a channel state for multiple input multiple output (MIMO) in a wireless local access network, the wireless apparatus comprising a processor configured to:
broadcast a channel request frame including an initiator field and a recipient set field, the initiator field indicating an address of the wireless apparatus, the recipient set field including a plurality of subfields indicating a plurality of recipients to prepare a channel response frame, each of the plurality of subfields including a recipient field indicating an identifier of each recipient, wherein the plurality of recipients receive independent data streams simultaneously over same channel bandwidth; and
sequentially receive, from each of the plurality of recipients, the channel response frame including the channel state for MIMO channel.
18. The wireless apparatus of claim 17, wherein the processor further configured to transmit, to the plurality of recipients, a null data packet frame to determine the channel state after broadcasting the channel request frame.
19. The wireless apparatus of claim 18, wherein a bandwidth of the channel response frame is equal to or narrower than a bandwidth of the null data packet frame.
20. The wireless apparatus of claim 18, wherein the channel request frame further includes a duration field indicating an estimated time required to transmit the null data packet frame and the channel response frame.
21. The wireless apparatus of claim 18, wherein the channel request frame further includes a receiver address field which is set to a broadcast address.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
forming an oxide layer on a top surface of a substrate;
forming a deep trench through the oxide layer and into the substrate;
forming a buried plate of a deep trench capacitor by doping sidewalls of the substrate exposed within the deep trench using an ion implantation technique, the oxide layer remains and protects a top surface of the substrate from being doped by the ion implantation;
forming a node dielectric along sidewalls and a bottom of the deep trench;
forming an inner electrode on top of the node dielectric within the deep trench;
forming an opening by recessing the node dielectric and the inner electrode; and
forming a dielectric cap by filling the opening with a dielectric material such that a top surface of the dielectric cap is substantially flush with the top surface of the oxide layer, and
bonding a III-V compound semiconductor to a top surface of the oxide layer, wherein the dielectric cap is in direct contact with the III-V compound semiconductor.
2. The method of claim 1, wherein the III-V compound semiconductor comprises gallium, arsenic, indium, or some combination thereof.
3. The method of claim 1, further comprising:
forming a III-V semiconductor device in the III-V compound semiconductor.
4. The method of claim 1, wherein the III-V semiconductor material comprises at least one element from Group 13 and at least one element from Group 15 of the Periodic Table of Elements.
5. The method of claim 1, wherein bonding the III-V compound semiconductor to the top surface of the oxide layer comprises:
growing a buffer layer on a donor wafer;
growing the III-V compound semiconductor on the buffer layer;
touching a top surface of the III-V compound semiconductor to the top surface of the oxide layer; and
removing the buffer layer and the donor wafer.
6. The method of claim 1, further comprising:
forming a node dielectric on top of the buried plate within the deep trench, the node dielectric extending along sidewalls of the oxide layer and along the sidewalls of the substrate.
7. The method of claim 1, further comprising:
forming an electrical connection between an inner electrode of the deep trench capacitor and a source-drain region of a III-V semiconductor device by forming a contact above and in direct contact with the inner electrode and the source-drain region.
8. A method comprising:
forming an oxide layer on a top of a substrate;
forming a deep trench through the oxide layer and into the substrate, the deep trench extending from an upper surface of the oxide layer down to a level within the substrate;
forming a buried plate of a deep trench capacitor by doping sidewalls of the substrate exposed within the deep trench using an ion implantation technique, the oxide layer remains and protects a top surface of the substrate from being doped by the ion implantation;
forming a node dielectric along sidewalls and a bottom of the deep trench;
forming an inner electrode on top of the node dielectric within the deep trench;
forming an opening by recessing the node dielectric and the inner electrode; and
forming a dielectric cap by filling the opening with a dielectric material such that a top surface of the dielectric cap is substantially flush with the top surface of the oxide layer,
bonding a III-V compound semiconductor to a top surface of the oxide layer, the dielectric cap being in direct contact with the III-V compound semiconductor; and
forming a III-V semiconductor device in the III-V compound semiconductor.
9. The method of claim 8, wherein bonding the III-V compound semiconductor to the top surface of the oxide layer comprises:
growing a buffer layer on a donor wafer;
growing the III-V compound semiconductor on the buffer layer;
touching a top surface of the III-V compound semiconductor to the top surface of the oxide layer; and
removing the buffer layer and the donor wafer.
10. The method of claim 8, wherein the III-V semiconductor material comprises at least one element from Group 13 of the Periodic Table of Elements and at least one element from Group 15 of the Periodic Table of Elements.
11. The method of claim 8, wherein the III-V compound semiconductor comprises gallium, arsenic, or some combination thereof.
12. The method of claim 8, wherein the III-V compound semiconductor comprises gallium, arsenic, indium, or some combination thereof.
13. The method of claim 8, further comprising:
forming an electric contact above and in direct contact with an inner electrode of the deep trench capacitor, the contact overlaps and is in direct contact with a source-drain region of the III-V semiconductor device.