1. A circuit simulation system, comprising:
a processor; and
a circuit simulator module that when executed causes the processor to simulate operation of an electronic circuit; the circuit simulator module comprising:
a field effect transistor (FET) model, the FET model configured to emulate a FET in a condition of dielectric breakdown, the FET model comprising models of:
a primary FET;
a first depletion mode FET and a second depletion mode FET connected between a gate and a drain of the primary FET;
wherein a gate and a drain of the first depletion mode FET are connected to the gate of the primary FET, and a gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.
2. The circuit simulation system of claim 1, wherein the FET model further comprises models of:
a first resistor through which the drain of the primary FET is connected to a source of the first depletion mode FET; and
a second resistor through which the gate of the primary FET is connected to a source of the second depletion mode FET.
3. The circuit simulation system of claim 1, wherein the FET model further comprises a model of a drain-source FET; wherein a gate of the drain-source FET is connected to the drain of the primary FET, a drain of the drain-source FET is connected via a resistor to a source of the primary FET, and a source of the drain-source FET is the source terminal of the primary FET.
4. The circuit simulation system of claim 1, wherein the FET model further comprises a model of a controllable tunneling diode; wherein a cathode of the diode is connected via a series resistor to a source of the primary FET, an anode of the diode is connected to the gate of the primary FET, and a control terminal of the diode is connected to the drain of the primary FET.
5. The circuit simulation system of claim 1, wherein the FET model further comprises models of:
a diode, an anode of the diode connected to the drain of the primary FET and a cathode of the diode connected, via a series resistor, to a P-well bias voltage of the primary FET; and
a resistor connected to the drain and P well bias voltage in parallel with the diode and series resistor.
6. The circuit simulation system of claim 1, wherein the FET model further comprises models of:
a first resistor connecting the gate and source of the primary FET;
a second resistor connecting the gate and drain of the primary FET; and
a third resistor connecting the drain and source of the primary FET.
7. The circuit simulation system of claim 1, wherein the models of the first depletion mode FET and the second depletion mode FET are configured to simulate saturation mode operation.
8. A non-transitory computer-readable storage medium encoded with a field effect transistor (FET) model that causes a computer to simulate:
a primary FET; and
two depletion mode FETs operating in saturation between a gate and a drain of the primary FET; wherein the depletion mode FETs provide a polarity symmetric gate current and emulate a power law exponent.
9. The computer-readable storage medium of claim 8, wherein the model causes the computer to simulate a voltage controller resistor interposed between a source and source terminal of the primary FET, the resistance of the voltage controlled resistor determined based on voltage at the drain of the primary FET.
10. The computer-readable storage medium of claim 8, wherein the model causes the computer to simulate a gate channel oxide tunneling diode connecting source and gate of the primary FET and controlled by the drain of the primary FET.
11. The computer-readable storage medium of claim 8, wherein the model causes the computer to simulate P-well bias current of the primary FET changing as an exponential function of gate voltage of the primary FET.
12. The computer-readable storage medium of claim 8, wherein the model causes the computer to simulate current flowing in gate and drain of the primary FET based on gate and drain of the primary FET being at equal voltage.
13. The computer-readable storage medium of claim 8, wherein the model causes the computer to simulate the power law exponent over a range of exponents from 1 to 2.
14. A method, comprising:
simulating, by a computer, operation of a field effect transistor (FET); the simulating comprising:
computing, by the computer, signal values based on a model of the FET, the model emulating:
a primary FET; and
a first and a second depletion mode FET operating in saturation between a gate and a drain of the primary FET; a gate and a drain of the first depletion mode FET being connected to the gate of the primary FET, and a gate and a drain of the second depletion mode FET being connected to the drain of the primary FET.
15. The method of claim 14, wherein the model emulates a first resistor through which the drain of the primary FET is connected to a source of the first depletion mode FET; and a second resistor through which the gate of the primary FET is connected to a source of the second depletion mode FET.
16. The method of claim 14, wherein the model emulates a drain-source FET disposed as a source terminal of the primary FET; wherein a gate of the drain-source FET is connected to the drain of the primary FET, a drain of the drain-source FET is connected via a resistor to a source of the primary FET, and a source of the drain-source FET is the source terminal of the primary FET.
17. The method of claim 14, wherein the model emulates a controllable tunneling diode; wherein a cathode of the diode is connected via a series resistor to a source of the primary FET, an anode of the diode is connected to the gate of the primary FET, and a control terminal of the diode is connected to the drain of the primary FET.
18. The method of claim 14, wherein the model emulates:
a diode, an anode of the diode connected to the drain of the primary FET and a cathode of the diode connected, via a series resistor, to a P-well bias voltage of the primary FET; and
a resistor connected to the drain and P well bias voltage in parallel with the diode and series resistor.
19. The method of claim 14, wherein the model emulates:
a first resistor connecting the gate and source of the primary FET;
a second resistor connecting the gate and drain of the primary FET; and
a third resistor connecting the drain and source of the primary FET.
20. A circuit comprising:
a primary field effect transistor (FET); and
a first depletion mode FET and a second depletion mode FET connected between a gate and a drain of the primary FET;
wherein a gate and a drain of the first depletion mode FET are connected to the gate of the primary FET, and a gate and a drain of the second depletion mode FET are connected to the drain of the primary FET;
wherein the first depletion mode FET and a second depletion mode FET operate in saturation.
21. The circuit of claim 20, further comprising:
a first resistor through which the drain of the primary FET is connected to a source of the first depletion mode FET; and
a second resistor through which the gate of the primary FET is connected to a source of the second depletion mode FET.
22. The circuit of claim 20, further comprising at least one of:
a drain-source FET, wherein a gate of the drain-source FET is connected to the drain of the primary FET, a drain of the drain-source FET is connected via a resistor to a source of the primary FET, and a source of the drain-source FET is the source terminal of the primary FET;
a controllable tunneling diode, wherein a cathode of the diode is connected via a series resistor to a source of the primary FET, an anode of the diode is connected to the gate of the primary FET, and a control terminal of the diode is connected to the drain of the primary FET;
a P-well bias network comprising:
a diode, an anode of the diode connected to the drain of the primary FET and a cathode of the diode connected, via a series resistor, to a P-well bias voltage of the primary FET; and
a resistor connected to the drain and P well bias voltage in parallel with the diode and series resistor; and
a resistor network comprising:
a first resistor connecting the gate and source of the primary FET;
a second resistor connecting the gate and drain of the primary FET; and
a third resistor connecting the drain and source of the primary FET.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An equalizer comprising:
a variable gain amplifier coupled to an input signal from a transmission medium and a variable gain control signal that applies a variable gain to the input signal to generate an equalizer core input signal having a pre-determined signal swing;
an equalizer core coupled to the equalizer core input signal that applies a frequency dependant gain to the variable gain amplifier output to compensate for attenuation of the input signal caused by losses incurred in the transmission medium and generates a core output signal;
a fixed-swing slicer coupled to the core output signal that converts the core output signal to a digital output signal having the pre-determined signal swing; and
a variable gain amplifier control loop (VG-Loop) coupled to the core output signal and the digital output signal that compares the core output signal with the digital output signal and generates the variable gain control signal;
wherein the VG-Loop comprises;
a first filter coupled to the core output signal that filters the core output signal to a frequency range at which the input signal incurs minimal attenuation from the transmission medium and generates a first low-frequency signal; and
a second filter coupled to the digital output signal that filters the digital output signal to a frequency range at which the input signal incurs minimal attenuation from the transmission medium and generates a second low-frequency signal;
wherein the first and second low-frequency signals are compared by the VG-Loop.
2. An equalizer comprising:
a variable gain amplifier coupled to an input signal from a transmission medium and a variable gain control signal that applies a variable gain to the input signal to generate an equalizer core input signal having a pre-determined signal swing;
an equalizer core coupled to the equalizer core input signal that applies a frequency dependant gain to the variable gain amplifier output to compensate for attenuation of the input signal caused by losses incurred in the transmission medium and generates a core output signal;
a fixed-swing slicer coupled to the core output signal that converts the core output signal to a digital output signal having the pre-determined signal swing; and
a variable gain amplifier control loop (VG-Loop) coupled to the core output signal and the digital output signal that compares the core output signal with the digital output signal and generates the variable gain control signal;
wherein the VG-Loop comprises:
a first envelope detector that detects an energy level in the core output signal and generates a first energy-level output; and
a second envelope detector that detects an energy level in the digital output signal and generates a second energy-level output;
wherein the VG-Loop compares the first and second energy-level outputs.
3. An adaptive equalizer, comprising:
a first core circuit comprising a transfer function circuit and a first amplifier coupled to the output of the transfer function circuit, the first amplifier operable to provide a variable gain in response to a first amplifier control signal, the first core circuit operable to receive a first input signal and the first amplifier control signal and generate a first core output signal;
a second amplifier operable to receive a transmission medium input signal and a second amplifier control signal and apply a variable gain to the transmission medium input signal in response to the second amplifier control signal and generate an amplified transmission medium input signal;
a summing circuit operable to receive the amplified transmission medium input signal and the first core output signal to generate an equalizer core output signal;
a slicer circuit operable to receive the equalizer core output signal and convert the equalizer core output signal to a digital output signal;
a first gain control loop circuit coupled to the summing circuit output and the slicer output and operable to process the equalizer core output signal and the digital output signal to generate the first amplifier control signal; and
a second gain control loop circuit coupled to the summing circuit output and the slicer output and operable to process the equalizer core output signal and the digital output signal to generate the second amplifier control signal.
4. The adaptive equalizer of claim 3, wherein the first input signal comprises the amplified transmission medium input signal.
5. The adaptive equalizer of claim 3, wherein the first input signal comprises the transmission medium input signal.
6. The adaptive equalizer of claim 3, wherein the first gain control loop circuit comprises a plurality of high-pass filters.
7. The adaptive equalizer of claim 3, wherein the second gain control loop circuit comprises a plurality of low-pass filters.
8. The adaptive equalizer of claim 3, wherein the slicer circuit comprises a fixed-swing slicer.