1. A head mounted display (HMD) comprising:
a camera unit configured to detect an external device, wherein the external device is a display device;
a display unit configured to display an augmented reality image;
a gaze detection unit configured to detect a gaze of a user; and
a processor configured to control the camera unit, the display unit and the gaze detection unit,
wherein the processor is further configured to:
detect the external device;
display the augmented reality image as a first mode, wherein the first mode is a mode in which a display position of the augmented reality image depends on a position of the external device;
change the first mode to a second mode when the gaze of the user to the augmented reality image is detected in the first mode, wherein the second mode is a mode in which the display position of the augmented reality image remains fixed even when the position of the external device is changed; and
execute a function corresponding to the augmented reality image when the augmented reality image and the external device are aligned in the second mode.
2. The HMD according to claim 1, wherein the processor is configured to execute the function corresponding to the augmented reality image when the augmented reality image and any one of at least one content image displayed on the external device are aligned in the second mode.
3. The HMD according to claim 2, wherein, when the function corresponding to the augmented reality image is executed, the processor is configured to display an execution augmented reality image for providing an execution screen of the function, associated with the aligned content image.
4. The HMD according to claim 1, wherein, when the function corresponding to the augmented reality image is executed, the processor is configured to display an execution augmented reality image for providing an execution screen of the function.
5. The HMD according to claim 4, wherein the display position of the execution augmented reality image depends on the display position of the augmented reality image.
6. The HMD according to claim 1, wherein the processor is configured to execute the function corresponding to the augmented reality image when the augmented reality image, the external device and the gaze of the user to the augmented reality image are aligned in the second mode.
7. The HMD according to claim 1, wherein the processor is configured to execute the function corresponding to the augmented reality image when the augmented reality image and the external device are aligned in the second mode during a predetermined period.
8. The HMD according to claim 1, further comprising a communication unit configured to communicate with the external device,
wherein, when the function corresponding to the augmented reality image is executed, the processor is further configured to transmit, to the external device, control information for controlling the external device to display an execution screen of the function on the display unit of the external device using the communication unit.
9. The HMD according to claim 1, wherein the processor is further configured to change to the first mode again when execution of the function corresponding to the augmented reality image is terminated.
10. The HMD according to claim 1, wherein the processor is configured to display the augmented reality image as the first mode when the gaze of the user to the external device is detected.
11. The HMD according to claim 1, wherein the processor is configured to:
when a first gaze of the user to a first gaze area of the augmented reality image is detected in the first mode, acquire a first gaze holding period when the first gaze is held,
change the first mode to the second mode when the first gaze holding period is greater than or equal to a first time period, and
retain the first mode when the first gaze holding period is less than the first time period.
12. The HMD according to claim 11, wherein the first gaze area of the augmented reality image is greater than a display area of the augmented reality image.
13. The HMD according to claim 11, wherein the processor is further configured to:
when a second gaze of the user into an external area of the first gaze area is detected in the second mode, acquire a second gaze holding period when the second gaze is held,
change the second mode to the first mode again when the second gaze holding period is greater than or equal to a second time period, and
retain the second mode when the second gaze holding period is less than the second time period.
14. The HMD according to claim 13, wherein the first gaze holding period and the second gaze holding period are different.
15. The HMD according to claim 13, wherein the first gaze holding period is greater than the second gaze holding period.
16. The HMD according to claim 11, wherein the processor is further configured to display the second gaze area of the augmented reality image when the first mode is changed to the second mode.
17. The HMD according to claim 16, wherein the second gaze area is wider than the first gaze area.
18. The HMD according to claim 16, wherein the processor is further configured to:
retain the second mode when the gaze of the user to the second gaze area is detected in the second mode, and
change the second mode to the first mode again when the gaze of the user to the external area of the second gaze area is detected in the second mode.
19. The HMD according to claim 16, wherein the processor is further configured to terminate display of the second gaze area when the second mode is changed to the first mode again.
20. A method for controlling a head mounted display (HMD), the method comprising:
detecting an external device, wherein the external device is a display device;
displaying an augmented reality image as a first mode, wherein the first mode is a mode in which a display position of the augmented reality image depends on a position of the external device;
changing the first mode to a second mode when the gaze of the user to the augmented reality image is detected in the first mode, wherein the second mode is a mode in which the display position of the augmented reality image remains fixed even when the position of the external device is changed; and
executing a function corresponding to the augmented reality image when the augmented reality image and the external device are aligned in the second mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A single poly non-volatile memory structure, which comprises:
a semiconductor substrate having a first and second active areas divided by an isolation region;
a control gate embedded in the first active area and doped with impurities;
a first floating gate formed upon the control gate;
a second floating gate formed upon the second active area;
a first doped region and second doped region formed at opposite two sides of the second floating gate in the second active area to establish a channel between the first doped region and the second doped region; and
a floating gate line connecting between the first floating gate and the second floating gate for allowing the first floating gate and the second floating gate in a same potential when the first floating gate generates the potential for responding to the voltage level of the control gate, thereby driving electrons ejecting from the first doped region and trapped into the second floating gate.
2. The memory structure of claim 1 further comprising a word line contacting with the control gate and insulated from the floating gate line.
3. The memory structure of claim 1 further comprising a bit line contacting with the second doped region and insulated from the floating gate line.
4. The memory structure of claim 2 and claim 3 further comprising a dielectric layer formed on a surface of the semiconductor substrate for servicing as insulation among the first floating gate, the second floating gate, the floating gate line, the word line, and the bit line.
5. The memory structure of claim 1 wherein the control gate is formed in an N-well of the semiconductor substrate and has a higher dosage of N-type impurity than the N-well does.
6. The memory structure of claim 5 wherein the dosage of the control gate is between about 1101521015 cm2.
7. The memory structure of claim 1 wherein the first floating gate comprises an oxide layer formed on the first active area and a polysilicon layer stacked on the oxide layer.
8. The memory structure of claim 7 further comprising a tungsten silicide layer stacked upon the polysilicon layer.
9. The memory structure of claim 1 wherein the second floating gate comprises an oxide layer formed on the first active area and a polysilicon layer stacked on the oxide layer.
10. The memory structure of claim 9 further comprising a tungsten silicide layer stacked upon the polysilicon layer.
11. A method for fabricating a single poly non-volatile memory structure comprising following steps:
providing a semiconductor substrate with a first active area and a second active area, the first active area being separated from the second active area by an isolation region;
forming a doped buried layer in the first active area;
forming a first floating gate on the doped buried layer of the first active area and a second floating gate on the second active area;
forming a first and second doped regions at opposite two sides of the second floating gate in the second active area; and
connecting the first floating gate and the second floating gate with a floating gate line made of conductive material.
12. The method of claim 11 further comprising following steps before forming the doped buried layer:
forming an oxide layer upon the first active area and the second active area; and
forming a polysilicon layer upon the oxide layer.
13. The method of claim 12 further comprising following steps before forming the first floating gate and the second floating gate:
forming a tungsten silicide layer upon the polysilicon layer;
lithographing a photoresist layer upon the tungsten silicide layer for defining the first floating gate and the second floating gate;
etching the tungsten silicide layer, polysilicon layer, and the oxide layer by employing the photoresist layer as an etching mask; and
stripping the photoresist layer.
14. The method of claim 11 further comprising following steps before connecting the first floating gate and the second floating gate:
forming a dielectric layer covering the first floating gate, the second floating, and a surface of the semiconductor substrate;
patterning the dielectric layer for defining contact holes of the first floating gate, the second floating gate;
forming a conductive layer upon the dielectric layer and;
patterning the conductive layer for shaping the floating gate line.
15. The method of claim 11 wherein the first active area is defined in an N-type doped region of the substrate.
16. The method of claim 1 1 wherein the second active area is defined in a P-type doped region of the substrate.
17. The method of claim 11 wherein the doped buried layer is formed by implanting N-type impurities into the first active area.
18. The method of claim 17 wherein the N-type impurities have a dosage between about 11015 21015 cm2.
19. The method of claim 11 wherein the first doped region and the second doped region are formed by implanting N-type impurities into the opposite two sides of the second floating gate in the second active area.
20. The method of claim 19 wherein the first doped region and the second doped region have a dosage between about 810121.51013 cm2.