1. A processing system, comprising:
a bus having a transmit channel;
a receiving component; and
a sending component configured to broadcast a payload to the receiving component over the transmit channel, interrupt the broadcast of the payload to signal a new bus operation to the receiving component over the transmit channel, and resume the broadcast of the payload over the transmit channel.
2. The processing system of claim 1 wherein the new bus operation comprises a read operation.
3. The processing system of claim 2 wherein the bus further comprises a receive channel, and wherein the receiving component is configured to broadcast a payload to the sending component over the receive channel in response to the signal to the receiving component for the read operation.
4. The processing system of claim 3 wherein the receiving component is further configured to broadcast at least a portion of the payload over the receive channel concurrently with the broadcast of at least a portion of the payload broadcast over the transmit channel by the sending component.
5. The processing system of claim 3 wherein the signal for the read operation comprises an address location and transfer qualifiers.
6. The processing system of claim 1 wherein the sending component is further configured to signal a write operation to the receiving component over the transmit channel prior to broadcasting the payload.
7. The processing system of claim 6 wherein the signal for the write operation comprises an address location and transfer qualifiers.
8. A processing system, comprising:
a bus having a transmit channel;
a receiving component; and
a sending component configured to broadcast a payload to the receiving component over the transmit channel, interrupt the broadcast of the payload for each new bus operation initiated during the payload broadcast up to a maximum number of interrupts, signal a different one of the new bus operations to the receiving component over the transmit channel during each of the interrupts, and resume the broadcast of the payload over the transmit channel following each of the interrupts.
9. The processing system of claim 8 wherein at least one of the new bus operations comprises a read operation.
10. The processing system of claim 8 wherein the maximum number of interrupts is programmable.
11. The processing system of claim 8 wherein the sending component is further configured to delay signaling to the receiving component each of the new bus operations initiated during the payload broadcast that occurs after the payload broadcast has been interrupted the maximum number of times.
12. The processing system of claim 8 wherein the sending component further comprises a counter, the sending component being further configured to load the counter with a value equal to the maximum number of interrupts, decrement the value each time the payload broadcast is interrupted, and complete the payload broadcast without interruption once the value reaches zero.
13. A processing system, comprising:
a bus having a transmit channel;
a receiving component; and
a sending component configured to broadcast a payload to the receiving component over the transmit channel, initiate a new bus operation during a time period following the beginning of the payload broadcast, allow the payload to be broadcasted without interruption during the time period, interrupt the broadcast of the payload to signal the new bus operation to the receiving component over the transmit channel following the time period if the payload broadcast extends beyond the time period, and resume the broadcast of the payload if interrupted.
14. The processing system of claim 13 wherein the new bus operation comprises a read operation.
15. The processing system of claim 13 wherein the sending component is further configured to interrupt the payload broadcast to signal the new bus operation to the receiving component only after a specific number of clock cycles after the payload broadcast begins.
16. The processing system of claim 15 wherein the specific number of clock cycles is programmable.
17. The processing system of claim 15 wherein the sending component further comprises a counter, the sending component being further configured to load the counter with a value equal to the specific number of clock cycles, decrement the value after each of the clock cycles after the payload broadcast begins, and interrupt the payload broadcast to signal the new bus operation to the receiving component only after the value reaches zero.
18. The processing system of claim 13 wherein the sending component is further configured to interrupt the payload broadcast to signal the new bus operation to the receiving component only after a specific number of payload data beats having been broadcast.
19. The processing system of claim 18 wherein the specific number of payload data beats is programmable.
20. The processing system of claim 18 wherein the sending component further comprises a counter, the sending component being further configured to load the counter with a value equal to the specific number of payload data beats, and interrupt the payload broadcast to signal the new bus operation to the receiving component only after the value reaches zero.
21. A processing system, comprising:
a bus having a transmit channel;
a receiving component; and
a sending component having means for broadcasting a payload to the receiving component over the transmit channel, means for interrupting the broadcast of the payload to signal a new bus operation to the receiving component over the transmit channel, and means for resuming the broadcast of the payload.
22. A method of communicating between a sending component and a receiving component over a bus having a transmit channel, the method comprising:
broadcasting from the sending component a payload to the receiving component over the transmit channel;
interrupting the broadcast of the payload to signal a new bus operation to the receiving component over the transmit channel; and
resuming the broadcast of the payload from the sending component to the receiving component over the transmit channel.
23. The method of claim 22 wherein the new bus operation comprises a read operation.
24. The method of claim 23 wherein the bus further comprises a receive channel, the method further comprising broadcasting from the receiving component a payload to the sending component over the receive channel in response to the signal to the receiving component for the read operation.
25. The method of claim 24 wherein the broadcast of at least a portion of the payload from the receiving component to the sending component over the receive channel occurs concurrently with at least a portion of the broadcast of the payload broadcast from the sending component to the receiving component over the transmit channel.
26. The method of claim 24 wherein the signal for the read operation comprises an address location and transfer qualifiers.
27. The method of claim 22 further comprising signaling a write operation to the receiving component over the transmit channel by the sending component prior to broadcasting the payload.
28. The method of claim 27 wherein the signaling for the write operation comprises an address location and transfer qualifiers.
29. A method of communicating between a sending component and a receiving component over a bus having a transmit channel, the method comprising:
broadcasting from the sending component a payload to the receiving component over the transmit channel;
interrupting the broadcast of the payload for each new bus operation initiated by the sending component during the payload broadcast up to a maximum number of interrupts;
signaling by the sending component a different one of the new bus operations to the receiving component over the transmit channel during each of the interrupts; and
resuming the broadcast of the payload by the sending component to the receiving component over the transmit channel following each of the interrupts.
30. The method of claim 29 wherein at least one of the new bus operations comprises a read operation.
31. The method of claim 29 wherein the maximum number of interrupts is programmable.
32. The method of claim 29 further comprising delaying signaling by the sending component to the receiving component each of the new bus operations initiated during the payload broadcast that occurs after the payload broadcast has been interrupted the maximum number of times.
33. The method of claim 29 wherein the sending component further comprises a counter, the method further comprising loading the counter with a value equal to the maximum number of interrupts, decrementing the value each time the payload broadcast is interrupted, and completing the payload broadcast without interruption once the value reaches zero.
34. A method of communicating between a sending component and a receiving component over a bus having a transmit channel, the method comprising:
broadcasting a payload from the sending component to the receiving component over the transmit channel during first and second time periods;
initiating a new bus operation during the first time period, the first time period following the beginning of the payload broadcast;
interrupting the broadcast of the payload to signal the new bus operation by the sending component to the receiving component over the transmit channel during the second time period, the second time period following the first time period; and
resuming the broadcast of the payload.
35. The method of claim 34 wherein the new bus operation comprises a read operation.
36. The method of claim 34 wherein the payload broadcast is interrupted in response to the initiation of the new bus operation only after a specific number of clock cycles following the beginning of the payload.
37. The method of claim 36 wherein the specific number of clock cycles is programmable.
38. The method of claim 36 wherein the sending component further comprises a counter, the method further comprising loading the counter with a value equal to the specific number of clock cycles, decrementing the value after each of the clock cycles after the payload broadcast begins, and interrupting the payload broadcast in response to the initiation of the new bus operation only after the value reaches zero.
39. The method of claim 34 wherein the payload broadcast is interrupted in response to the initiation of the new bus operation only after a specific number of payload data beats have been broadcasted.
40. The method of claim 39 wherein the specific number of clock cycles is programmable.
41. The method of claim 39 wherein the sending component further comprises a counter, the method further comprising loading the counter with a value equal to the specific payload data beats, decrementing the value after each of the payload data beats is broadcasted, and interrupting the payload broadcast in response to the initiation of the new bus operation only after the value reaches zero.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device fabrication method having enhanced control in recessing processes comprising:
forming a structure;
preparing a limited amount of the structure for removal, wherein the limited amount of the structure has a depth of less than ten atomic layers; and
performing a removal process to remove the limited amount of the structure; and
repeating the preparing and the performing to form a recess at a peripheral portion of the structure.
2. The method of claim 1 wherein the limited amount of the structure is prepared for removal by performing a surface treatment process that transforms an exposed surface of the structure to an intermediate removable layer having a thickness of less than ten atomic layers.
3. The method of claim 2 wherein the intermediate removable layer is an oxidized layer, wherein transforming includes oxidizing the exposed surface of the structure to create the oxidized layer, and wherein the removal process is performed by etching the oxidized layer.
4. The method of claim 2 wherein the transforming happens intentionally at a rate at least as rapid as the removal rate.
5. The method of claim 2 wherein the surface treatment process and removal process are performed concurrently or in alternate cycles.
6. The method of claim 1 wherein the limited amount of the structure is prepared for removal by performing a surface treatment process that prepares an exposed surface of the structure for transformation to an intermediate removable layer; wherein performing the surface treatment process comprises depositing a meta-stable film of controlled thickness on the exposed surface of the structure; and wherein the removal process is performed by decomposing the meta-stable layer to generate etching of the exposed surface of the structure.
7. The method of claim 6 wherein the deposited meta-stable film thickness is one monolayer.
8. The method of claim 1 wherein forming the structure comprises forming the structure of a metal or a semiconductor material.
9. A semiconductor device fabrication method comprising:
forming a replacement gate electrode over a substrate;
preparing a limited amount of the replacement gate electrode for removal;
performing a removal process to remove the limited amount of the replacement gate electrode;
repeating the preparing and the performing to form a recess at a peripheral portion of the replacement gate electrode;
depositing a dielectric layer in the recess;
forming a insulating cap on top of the gate electrode and the dielectric layer and forming a contact.
10. The method of claim 9 wherein preparing comprises preparing the limited amount having a depth of less than ten atomic layers.
11. The method of claim 9 wherein the limited amount of the replacement gate electrode is prepared by performing a surface treatment process that transforms an exposed surface of the replacement gate electrode to an intermediate removable layer.
12. The method of claim 11 wherein the intermediate removable layer is an oxidized layer, and wherein transforming includes oxidizing the exposed surface of the replacement gate electrode to create the oxidized layer.
13. The method of claim 11 wherein the removal process is performed by etching the intermediate removable layer.
14. The method of claim 13 wherein workfunction metals are etched while etching the intermediate removable layer.
15. The method of claim 11 wherein the surface treatment process and removal process are performed concurrently.
16. The method of claim 11 wherein the surface treatment process and removal process are performed in alternate cycles.
17. The method of claim 9 wherein the limited amount of the replacement gate electrode is prepared by performing a surface treatment process that prepares an exposed surface of the replacement gate electrode for transformation to an intermediate removable layer, wherein performing the surface treatment process comprises depositing a meta-stable film of controlled thickness on the exposed surface of the replacement gate electrode, and wherein the removal process is performed by decomposing the meta-stable layer to generate removal of the exposed surface of the replacement gate electrode.
18. The method of claim 9 wherein forming the replacement gate electrode over a substrate comprises forming the replacement gate electrode of a metal or semiconductor materials.
19. The method of claim 9 wherein forming the replacement gate electrode comprises:
forming a removable gate electrode over the substrate;
removing the removable gate electrode to define an opening; and
forming the replacement gate electrode in the opening.
20. A semiconductor device fabrication method comprising:
forming a removable gate electrode over a substrate, the removable gate electrode including polysilicon;
forming a hardmask over the polysilicon;
forming spacers on side surfaces of the removable gate electrode;
forming a silicide on the substrate;
depositing an SAC stop layer over the hardmask layer, the spacers, and the silicide;
depositing an isolation material over the SAC stop layer;
removing the hardmask layer and the polysilicon from the removable gate electrode to form an opening;
depositing a metal lining in the opening;
depositing a fill on the metal lining in the opening to form a replacement gate electrode;
preparing a limited amount of the replacement gate electrode for removal;
performing a removal process to remove the limited amount of the replacement gate electrode;
repeating the preparing and the performing to form a recess at an upper portion of the replacement gate electrode;
depositing a dielectric layer in the recess; and
forming a self-aligned contact.