1. A computer system comprising a processor and a storage device, the processor programmed to:
(a) perform an initial read of a code word from a plurality of cells of the storage device using one or more threshold levels;
(b) adjust the one or more threshold levels to obtain one or more current threshold levels based on an iteration count;
(c) retry reading the code word from the plurality of cells of the storage device using the one or more current threshold levels;
(d) attempt to decode the code word using a log likelihood ratio (LLR) table of a plurality of LLR tables, outcomes of the initial read (a) and one or more retry readings (d), each LLR table of the plurality of LLR tables corresponding to the iteration count; and
(e) if attempting to decode the code word at (c) is unsuccessful and the iteration count is less than a maximum iteration count, repeat steps (b) through (e).
2. The computer system of claim 1, wherein all entries of the plurality of LLR tables are fixed prior to performing (b) through (e) and are not changed between iterations of (b) through (3).
3. The computer system of claim 1, wherein each LLR table of the plurality of LLR tables includes entries for less than all possible outcomes of outcomes of retrying reading the code word from the plurality of cells at (c) for the iteration count corresponding to the each LLR table.
4. The computer system of claim 3, wherein the entries of each LLR table of the plurality of LLR tables include entries selected according to probable outcomes for the current threshold levels for the iteration count corresponding to the each LLR table.
5. The computer system of claim 1, wherein the storage device is a NAND flash device.
6. The computer system of claim 1, wherein the storage device is a multi-level cell NAND flash device.
7. The computer system of claim 1, wherein the storage device is a three-level cell NAND flash device.
8. The computer system of claim 1, wherein adjusting the one or more threshold levels to obtain the one or more current threshold levels based on the iteration count comprises adjusting a plurality of thresholds according to two or more different step sizes.
9. The computer system of claim 1, wherein the maximum iteration count is 6.
10. The computer system of claim 1, wherein attempting to decode the code word comprises performing low density parity check (LDPC) decoding.
11. A method comprising:
(a) performing an initial read of a code word from a plurality of cells of the storage device using one or more threshold levels;
(b) adjusting the one or more threshold levels to obtain one or more current threshold levels based on an iteration count, each of the one or more current thresholds for each value of the iteration count having a value different from the one or more current thresholds;
(c) retrying reading the code word from the plurality of cells of the storage device using the one or more current threshold levels;
(d) attempting to decode the code word using a log likelihood ratio (LLR) table of a plurality of LLR tables, outcomes of the initial read (a) and one or more retry readings (c), each LLR table of the plurality of LLR tables corresponding to the iteration count; and
(e) if attempting to decode the code word at (d) is unsuccessful and the iteration count is less than a maximum iteration count, iterating steps (b) through (d).
12. The method of claim 11, wherein all entries of the plurality of LLR tables are fixed prior to performing (b) through (e).
13. The method of claim 11, wherein each LLR table of the plurality of LLR tables includes entries for less than all possible outcomes of outcomes of retrying reading the code word from the plurality of cells at (c) for the iteration count corresponding to the each LLR table.
14. The method of claim 13, wherein the entries of each LLR table of the plurality of LLR tables include entries selected according to probable outcomes for the current threshold levels for the iteration count corresponding to the each LLR table.
15. The method of claim 1, wherein the storage device is a NAND flash device.
16. The method of claim 1, wherein the storage device is a multi-level cell NAND flash device.
17. The method of claim 1, wherein the storage device is a three-level cell NAND flash device.
18. The method of claim 1, wherein adjusting the one or more threshold levels to obtain the one or more current threshold levels based on the iteration count comprises adjusting a plurality of thresholds according to two or more different step sizes.
19. The method of claim 1, wherein the maximum iteration count is 6.
20. The method of claim 1, wherein attempting to decode the code word comprises performing low density parity check (LDPC) decoding.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A photosensor for use in an imaging device formed in a single integrated circuit, said photosensor comprising:
a doped layer of a first conductivity type formed in a substrate;
a charge collection region formed in said doped layer;
a floating diffusion region of a second conductivity type for receiving charge from said charge collection region; and
a charge storage capacitor electrically and directly connected to said floating diffusion region by an electrical contact, said charge storage capacitor being formed at least partially over one of a field oxide region and an active area of said photosensor.
2. The photosensor according to claim 1, wherein said charge storage capacitor is formed fully over said field oxide region.
3. The photosensor according to claim 1, wherein said charge storage capacitor is formed fully over said active area.
4. The photosensor according to claim 1, wherein said charge storage capacitor is formed partially over said field oxide region.
5. The photosensor according to claim 1, wherein said charge storage capacitor is formed partially over said active area.
6. The photosensor according to claim 1, wherein said storage capacitor is a trench capacitor.
7. The photosensor according to claim 1, wherein said storage capacitor is a stacked capacitor.
8. The photosensor according to claim 1, wherein said storage capacitor is a metal capacitor.
9. The photosensor according to claim 1, wherein said storage capacitor is an HSG capacitor.
10. The photosensor according to claim 1, wherein said storage capacitor is a container capacitor.
11. The photosensor according to claim 1, wherein said storage capacitor is a flat plate capacitor.
12. The photosensor according to claim 1, wherein said storage capacitor is a flat plate capacitor including a first electrode, a second electrode and a insulating layer between said first and second electrodes.
13. The photosensor according to claim 12, wherein said floating diffusion region is connected to one of said first and second electrodes by said electrical contact.
14. The photosensor according to claim 12, wherein one of said first and second electrodes is further connected to a gate of a transfer transistor.
15. The photosensor according to claim 12, wherein said first and second electrodes are independently selected from the group consisting of doped polysilicon, hemispherical grained polysilicon, TiN, polyWSix, polyTiSi2, and polyWNxW.
16. The photosensor according to claim 1, wherein said first conductivity type is p-type, and said second conductivity type is n-type.
17. The photosensor according to claim 1, further comprising a source follower transistor for outputting charge accumulated in said floating diffusion region which has been transferred to said floating diffusion region, wherein the gate of said source follower transistor is formed adjacent said floating diffusion region.
18. The photosensor according to claim 17, wherein an electrode of said storage capacitor is further connected to the gate of said source follower transistor.
19. The photosensor according to claim 1 further comprising a reset transistor.
20. The photosensor according to claim 19, wherein an electrode of said storage capacitor is further connected to a gate of said reset transistor.
21. The photosensor according to claim 1 further comprising a global shutter transistor.
22. The photosensor according to claim 21, wherein an electrode of said storage capacitor is further connected to a gate of said global shutter transistor.
23. The photosensor according to claim 1, wherein said photosensor is used in a CMOS imager.