1. A synchronous semiconductor memory device that includes a burst read mode of operation having a plurality of internal burst cycles, comprising:
a memory cell array that stores data information;
an address generating circuit that operates synchronized with a clock signal and sequentially generates an internal address for the burst read mode of operation in response to an external address;
a data read circuit that reads out burst data from the memory cell array based on a part of the internal address, the burst data being outputted during the respective internal burst cycles;
a read control circuit that operates responsive to a read enable signal and controls a read operation of the data read circuit at a transition of either one of the external address and the internal address;
a burst control circuit that operates responsive to a burst enable signal and generates a latch enable signal synchronized with the clock signal;
a data register that latches the burst data read out through the read circuit in response to the latch enable signal and sequentially outputs the latched burst data in response to another part of the internal address; and
a detection means that detects whether the internal address reaches a burst address set corresponding to the last one of the internal burst cycles and generates the burst enable signal and the read enable signal for controlling the burst control circuit and the read control circuit based on a detection result.
2. The synchronous semiconductor memory device according to claim 1, wherein the address generating circuit generates an internal address every cycle of the clock signal, and the read control circuit makes the data read circuit operate every clock cycle corresponding to a burst length of each of the internal burst cycles.
3. The synchronous semiconductor memory device according to claim 1, wherein when an internal address reaches a burst address set corresponding to the last internal burst cycles, the detection means makes the burst enable signal inactive after burst data of the last burst address set is outputted.
4. The synchronous semiconductor memory device according to claim 3, wherein when an internal address reaches a burst address set corresponding to the last internal burst cycles, the detection means makes the read enable signal inactive before the last internal burst cycle.
5. A multi-chip system that includes a burst read mode of operation having a plurality of internal burst cycles, comprising:
a clock line that transfers a clock signal;
a first bus that transfers control signals;
a second bus that selectively transfers data and an address;
a first semiconductor memory device that is connected to the clock line and the first bus; and
a second semiconductor memory device that is connected to the clock line and the second bus,
wherein each of the first and second semiconductor memory devices comprise
a memory cell array that stores data information;
an address generating circuit that operates synchronized with the clock signal and sequentially generates an internal address for the burst read mode of operation in response to an external address;
a data read circuit that reads out burst data from the memory cell array based on a part of the internal address, the burst data being outputted during the respective internal burst cycles;
a read control circuit that operates responsive to a read enable signal and controls a read operation of the data read circuit at a transition of either one of the external address and the internal address;
a burst control circuit that operates responsive to a burst enable signal and generates a latch enable signal synchronized with the clock signal;
a data register that latches the burst data read out through the read circuit in response to the latch enable signal and sequentially outputs the latched burst data in response to another part of the internal address; and
detection means that detect whether the internal address reaches a burst address set corresponding to the last one of the internal burst cycles and generates the burst enable signal and the read enable signal for controlling the burst control circuit and the read control circuit based on a detection result.
6. The multi-chip system according to claim 5, wherein the address generating circuit generates an internal address every cycle of the clock signal, and the read control circuit makes the data read circuit operate every clock cycle corresponding to a burst length of each of the internal burst cycles.
7. The multi-chip system according to claim 6, wherein the detection means includes:
a first flag signal generating circuit that generates a first flag signal indicating whether a corresponding semiconductor memory device is mounted in the multi-chip system;
a second flag signal generating circuit that generates a second flag signal indicating whether the corresponding semiconductor memory device belongs to an upper address region of the multi-chip system; and
a boundary detecting circuit that operates responsive to the first and second flag signals and detects whether the one of the internal address reaches a burst address set corresponding to the last internal burst cycle, the boundary detecting circuit generating the read enable signal and the burst enable signal based on a detection result.
8. The multi-chip system according to claim 7, wherein in the case that an address region of the first semiconductor memory device belongs to a lower one of an address region of the multi-chip system, when the internal address reaches the burst address set corresponding to the last internal burst cycle, the boundary detecting circuit makes the read enable signal inactive before the last internal burst cycle and the burst enable signal inactive after the last internal burst cycle.
9. The multi-chip system according to claim 7, wherein in the case that an address region of the second semiconductor memory device belongs to an upper one of an address region of the multi-chip system, when the internal address reaches the burst address set corresponding to the last internal burst cycle, the boundary detecting circuit makes the read enable signal active before the last internal burst cycle and the burst enable signal active after the last internal burst cycle.
10. The multi-chip system according to claim 7, wherein both the first flag signal generating circuit and the second flag signal generating circuit comprise a bonding pad.
11. The multi-chip system according to claim 7, wherein both the first flag signal generating circuit and the second flag signal generating circuit comprise a laser fuse.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor package comprising:
a substrate having at least one cavity formed in a side surface thereof and an electrode provided within the cavity;
at least one electronic component mounted on a surface of the substrate;
a mold part sealing the electronic component and having insulating properties; and
a shield part attached to the mold part to cover an outer surface of the mold part, electrically connected to the electrode provided within the cavity, and having conductive properties.
2. The semiconductor package of claim 1, wherein the shield part is provided to extend along the side surface of the substrate.
3. The semiconductor package of claim 1, wherein the electrode is provided on at least one surface of the cavity.
4. The semiconductor package of claim 1, wherein the electrode is formed by filling the cavity with a conductive material.
5. The semiconductor package of claim 1, wherein the cavity is elongated in the side surface of the substrate in a lengthwise direction.
6. A method of manufacturing a semiconductor package, the method comprising:
preparing a substrate having at least one cavity and an electrode provided within the cavity;
mounting an electronic component on an upper surface of the substrate;
forming a mold part having insulating properties to seal the electronic component; and
forming a shield part on an outer surface of the mold part, the shield part being electrically connected to the electrode provided within the cavity and having conductive properties.
7. The method of claim 6, wherein the substrate has the cavity formed in at least one side surface thereof.
8. The method of claim 6, wherein the shield part is formed to extend up to the side surface of the substrate.
9. The method of claim 6, wherein the substrate is shaped as a strip including a plurality of individual semiconductor package areas.
10. The method of claim 9, wherein the substrate has the cavity formed in the inside thereof along a boundary dividing the individual semiconductor package areas.
11. The method of claim 10, wherein the electronic component is mounted on each of the individual semiconductor package areas.
12. The method of claim 11, wherein the mold part is integrally formed to seal all the individual semiconductor package areas.
13. The method of claim 12, wherein the forming of the shield part comprises:
dividing the substrate having the mold part formed thereon into individual semiconductor packages by cutting the substrate according to the individual semiconductor package areas; and
forming the shield part on each of the individual semiconductor packages.
14. The method of claim 13, wherein the dividing of the substrate into the individual semiconductor packages causes the cavity to be exposed through the side surface of the substrate being cut.
15. The method of claim 13, wherein the forming of the shield part on each of the individual semiconductor packages is performed by spray coating.
16. The method of claim 12, wherein the forming of the shield part comprises:
a first cutting process cutting the substrate having the mold part formed thereon according to the individual semiconductor package areas only up to a position where the cavity is formed;
forming the shield part on the substrate subjected to the first cutting process; and
a second cutting process completely cutting the substrate having the shield formed thereon.
17. The method of claim 16, wherein the forming of the shield part on the substrate subjected to the first cutting process comprises forming the shield part on the outer surface of the mold part and in the cavity exposed through the first cutting process.
18. The method of claim 16, wherein the second cutting process is performed to cause a cut surface of the substrate and a vertical outer surface of the shield part to be positioned on different planes.
19. The method of claim 16, wherein the forming of the shield part on the substrate subjected to the first cutting process is performed by any one of spray coating or screen printing.