1. A method of fabricating a nanopore structure with nanopore for sensing a portion of a nanoscale moiety, comprising:
(a) providing a first electrode having a portion of a nanopore there through, the portion of the nanopore defining an electrode edge;
(b) depositing an insulator on the first electrode adjacent to the nanopore, the insulator having a portion of the nanopore there through and defining an insulator edge, the insulator edge overhanging the first electrode edge; and
(c) depositing a second electrode on the insulator adjacent to the nanopore, the second electrode having a portion of the nanopore there through and defining the second electrode edge, the second electrode edge overhanging the insulator edge to define the nanopore structure.
2. A method of fabricating a nanopore structure as recited in claim 1, wherein at least one deposition step is performed by angled line of sight deposition.
3. A method of fabricating a nanopore structure as recited in claim 1, wherein each step is performed by angled line of sight deposition.
4. A method of making a layered nanopore structure, comprising:
(a) providing a substrate with a surface and a portion of a nanopore there through;
(b) tilting the substrate surface to an angle defined between horizontal and the substrate surface;
(c) rotating the substrate at the tilted angle;
(d) depositing a second electrode on the substrate surface adjacent to the nanopore to define a second electrode edge;
(e) tilting the substrate surface to an angle defined between the horizontal and the substrate surface;
(f) rotating the substrate and second electrode at the tilted angle;
(g) depositing a first insulator on the second electrode adjacent to the nanopore to define a first insulator edge;
(h) tilting the substrate surface at an angle defined between horizontal and the substrate surface;
(i) rotating the substrate at the tilted angle;
(j) depositing a first electrode on the substrate surface adjacent to the nanopore to define a first electrode edge wherein the first electrode edge, the first insulator edge and the second electrode edges define a layered nanopore structure.
5. A method as recited in claim 4, wherein the angle defined in step (b) is smaller than the angle defined in step (e).
6. A method as recited in claim 4, wherein the angle defined in step (e) is smaller than the angle defined in step (h).
7. A method as recited in claim 4, wherein the angle defined in step (b) is 45 degrees.
8. A method as recited in claim 4, wherein the angle defined in step (e) is 35 degrees.
9. A method as recited in claim 4, wherein the angled defined in step (h) is 25 degrees.
10. A method of making a layered nanopore structure, comprising:
(a) etching a silicon substrate to form a window of silicon nitride on silicon dioxide;
(b) etching the silicon nitride to form a window of silicon dioxide;
(c) forming a nanopore using focused ion beam drilling followed by argon ion beam sculpting;
(d) depositing a first electrode on the substrate adjacent to the nanopore and defining the first electrode by photolithography;
(e) depositing a first insulator on the first electrode adjacent to the nanopore and defining the first insulator layer by photolithography;
(f) depositing a second electrode on the first insulator adjacent to the nanopore and defining the second electrode by photolithography;
(g) depositing an optional insulator on the second electrode adjacent to the nanopore and defining the optional insulator by photolithography;
(h) depositing an aluminum interconnect layer on the optional insulator and defining the aluminum interconnect layer by photolithography; and
(i) depositing an insulator substrate on the aluminum interconnect layer and defining the insulator substrate layer by photolithography.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resistive memory driving method comprising:
applying an initial voltage to a plurality of word lines and a plurality of bit lines;
setting the plurality of word lines and the plurality of bit lines to a floating state; and
applying an operating voltage set according to a mode of operation to a selected word line among the plurality of word lines and a selected bit line among the plurality of bit lines,
wherein applying the operating voltage set comprises applying read pulses having read voltage levels for reading operation to the selected word line and the selected bit line, and
wherein widths of the read pulses are greater than widths of voltage pulses that are applied to the selected word line and the selected bit line for writing operation.
2. The resistive memory driving method of claim 1, wherein applying the initial voltage comprises applying a voltage of a level of a ground voltage to the plurality of word lines and the plurality of bit lines.
3. The resistive memory driving method of claim 1, wherein applying the operating voltage set further comprises applying voltage pulses to the selected word line and the selected bit line, each of the voltage pulses having a width less than or equal to a line delay period.
4. The resistive memory driving method of claim 3, wherein the line delay period comprises a product of resistance values and capacitance values of the selected word line and the selected bit line.
5. The resistive memory driving method of claim 3, wherein the line delay period comprises a time constant, which is a product of resistance and capacitance of unselected word lines among the plurality of word lines and unselected bit lines among the plurality of bit lines.
6. The resistive memory driving method of claim 3, wherein applying the voltage pulses comprises applying set pulses having set voltage levels for writing operation.
7. The resistive memory driving method of claim 3, wherein applying the voltage pulses comprises applying reset pulses having reset voltage levels for writing operation.
8. The resistive memory driving method of claim 3, wherein applying the voltage pulses comprises applying forming pulses having a forming voltage level set for forming operation.
9. A resistive memory device comprising:
a memory cell array including word lines, bit lines and memory cells in respective ones of intersections of each of the word lines and each of the bit lines; and
a control circuit configured to apply an initial voltage to the word lines and the bit lines and then to apply an operating voltage set according to a mode of operation to a selected word line among the word lines and a selected bit line among the bit lines within a line delay period while unselected word lines among the word lines and unselected bit lines among the bit lines being electrically floated, wherein the line delay period comprises a time constant, which is a product of resistance and capacitance of one word line among the word lines and one bit line among the bit lines.
10. The resistive memory device of claim 9, wherein the operating voltage set according to a mode of operation comprises voltage pulses, each of the voltage pulses having a width less than or equal to the line delay period.
11. The resistive memory device of claim 10, wherein the voltage pulses comprises set pulses having set voltage levels, reset pulses having reset voltage levels, or read pulses having read voltage levels.
12. The resistive memory device of claim 11, wherein widths of the read pulses are greater than widths of the set pulses or widths of the reset pulses.
13. A method of programming and reading a nonvolatile memory device comprising:
applying a first voltage pulse to a selected word line and applying a second voltage pulse to a selected bit line to program or read a selected cell identified by the selected word line and selected bit line, wherein each of the first and second voltage pulses has a duration equal to or less than a line delay period associated with the selected word line and selected bit line, and wherein the line delay is a time constant comprising a product of a resistance and a capacitance of the selected word line and a resistance and a capacitance of the selected bit line.
14. The method of claim 13, further comprising:
setting a plurality of word lines comprising the selected word line and a plurality of bit lines comprising the selected bit line to a floating state before applying the first and second voltage pulses; and
maintaining unselected word lines among the plurality of word lines and unselected bit lines among the plurality of bit lines in the floating state while applying the first and second voltage pulses.
15. The method of claim 14, further comprising:
applying a first initial voltage to the plurality of word lines and applying a second initial voltage to the plurality of bit lines before setting the plurality of word lines and the plurality of bit lines to the floating state.
16. The method of claim 13, wherein the first voltage pulse has an amplitude equal to that of the second voltage pulse and the first voltage pulse has polarity opposite of that of the second voltage pulse.
17. The method of claim 13, wherein the first voltage pulse that is applied to read the selected cell has a first width and the first voltage pulse that is applied to program the selected cell has a second width that is less than the first width.