1. A semiconductor device comprising:
a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar provided underneath the first silicon pillar; and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the second silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region; and
the third silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein:
the first-conductive type impurity region of the second silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the second silicon pillar; and
the first-conductive type impurity region of the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the third silicon pillar.
2. A semiconductor device comprising:
a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar underneath the first silicon pillar; and
a third silicon pillar on a top of the first silicon pillar,
wherein:
the second silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region; and
the third silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein:
each of the first-conductive type impurity region of the second silicon pillar and the first-conductive type impurity region of the third silicon pillar has a length sufficient to accommodate the second-conductive type high-concentration impurity region of the second silicon pillar and the second-conductive type high-concentration impurity region of the third silicon pillar.
3. The semiconductor device as defined in claim 1, which satisfies the following relations (1) and (2):
Ls
>
Ts
4
,
(
1
)
wherein: Ls and Ts are, respectively, a length and a diameter of the first-conductive type impurity region of the third silicon pillar on a source side; and
Ld
>
Td
4
,
(
2
)
wherein Ld and Td are, respectively, a length and a diameter of the first-conductive type impurity region of the second silicon pillar on a drain side.
4. The semiconductor device as defined in claim 2, which satisfies the following relation:
tan
\ue8a0
(
\u03c0
36
)
\xb7
Tspace
–
(
Lg
+
Ljs
+
Ljd
)
>
Ls
+
Ld
,
wherein:
Tspace is a distance between adjacent two of a plurality of the semiconductor devices formed on a silicon substrate;
Lg is a length of the gate;
Ljd is a depth of the second-conductive type high-concentration impurity region formed in the second silicon pillar to serve as a drain;
Ljs is a depth of the second-conductive type high-concentration impurity region formed in the third silicon pillar to serve as a source;
Ld is a length of the first-conductive type impurity region of the second silicon pillar; and
Ls is a length of the first-conductive type impurity region of the third silicon pillar.
5. A semiconductor device comprising:
a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar underneath the first silicon pillar; and
a third silicon pillar on a top of the first silicon pillar,
wherein:
the second silicon pillar comprises a second-conductive type high-concentration impurity region; and
the third silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein the first-conductive type impurity region of the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the third silicon pillar.
6. A semiconductor device comprising:
a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar underneath the first silicon pillar; and
a third silicon pillar on a top of the first silicon pillar,
wherein:
the second silicon pillar comprises a second-conductive type high-concentration impurity region; and
the third silicon pillar has a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein the first-conductive type impurity region of the third silicon pillar has a length sufficient to accommodate the second-conductive type high-concentration impurity region of the second silicon pillar and the second-conductive type high-concentration impurity region of the third silicon pillar.
7. The semiconductor device as defined in claim 5, which satisfies the following relation:
Ls
>
Ts
4
,
wherein Ls and Ts are, respectively, a length and a diameter of the first-conductive type impurity region of the third silicon pillar on a source side.
8. The semiconductor device as defined in claim 6, which satisfies the following relation:
wherein:
Tspace is a distance between adjacent two of a plurality of the semiconductor devices formed on a silicon substrate;
Lg is a length of the gate;
Ljd is a height of the second-conductive type high-concentration impurity region formed in the second silicon pillar to serve as a drain;
Ljs is a depth of the second-conductive type high-concentration impurity region formed in the third silicon pillar to serve as a source; and
Ls is a length of the first-conductive type impurity region of the third silicon pillar.
9-12. (canceled)
13. The semiconductor device as defined in claim 1, wherein:
the first silicon pillar comprises a high resistance region;
the first-conductive type impurity region of the second silicon pillar comprises a high resistance region; and
the first-conductive type impurity region of the third silicon pillar comprises a high resistance region.
14. The semiconductor device as defined in claim 2, wherein:
the first silicon pillar comprises a high resistance region;
the first-conductive type impurity region of the second silicon pillar comprises a high resistance region; and
the first-conductive type impurity region of the third silicon pillar comprises a high resistance region.
15. The semiconductor device as defined in claim 5, wherein:
the first silicon pillar comprises a high resistance region;
the first-conductive type impurity region of the second silicon pillar comprises a high resistance region; and
the first-conductive type impurity region of the third silicon pillar comprises a high resistance region.
16. The semiconductor device as defined in claim 6, wherein:
the first silicon pillar comprises a high resistance region;
the first-conductive type impurity region of the second silicon pillar comprises a high resistance region; and
the first-conductive type impurity region of the third silicon pillar comprises a high resistance region.
17-18. (canceled)
19. The semiconductor device as defined in claim 1, wherein each of the first-conductive type impurity region of the second silicon pillar and the first-conductive type impurity region of the third silicon pillar has a diameter greater than that of the first silicon pillar.
20. The semiconductor device as defined in claim 2, wherein each of the first-conductive type impurity region of the second silicon pillar and the first-conductive type impurity region of the third silicon pillar has a diameter greater than that of the first silicon pillar.
21. The semiconductor device as defined in claim 5, wherein each of the first-conductive type impurity region of the second silicon pillar and the first-conductive type impurity region of the third silicon pillar has a diameter greater than that of the first silicon pillar.
22. The semiconductor device as defined in claim 6, wherein each of the first-conductive type impurity region of the second silicon pillar and the first-conductive type impurity region of the third silicon pillar has a diameter greater than that of the first silicon pillar.
23-32. (canceled)
33. The semiconductor device as defined in claim 1, wherein the first silicon pillar comprises a high resistance region or a first-conductive type impurity region, and wherein:
the first-conductive type impurity region of the second silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less; and
the first-conductive type impurity region of the third silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less.
34. The semiconductor device as defined in claim 2, wherein the first silicon pillar comprises a high resistance region or a first-conductive type impurity region, and wherein:
the first-conductive type impurity region of the second silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less; and
the first-conductive type impurity region of the third silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less.
35. The semiconductor device as defined in claim 5, wherein the first silicon pillar comprises a high resistance region or a first-conductive type impurity region, and wherein:
the first-conductive type impurity region of the second silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less; and
the first-conductive type impurity region of the third silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less.
36. The semiconductor device as defined in claim 6, wherein the first silicon pillar comprises a high resistance region or a first-conductive type impurity region, and wherein:
the first-conductive type impurity region of the second silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less; and
the first-conductive type impurity region of the third silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less.
37. A semiconductor device comprising:
a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric and a gate depletion layer extending in the first-conductive type first silicon pillar;
a second silicon pillar underneath the first silicon pillar; and
a third silicon pillar on a top of the first silicon pillar, and comprising a second-conductive type high-concentration impurity region,
wherein the second silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and includes a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region of the second silicon pillar,
and wherein the first-conductive type impurity region has a length greater than that of a sourcedrain depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of the second silicon pillar and the sourcedrain depletion layer is spaced apart from the gate depletion layer,
wherein the first silicon pillar comprises a high resistance region or a first-conductive type impurity region, and wherein:
the first-conductive type impurity region of the second silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less; and
the first-conductive type impurity region of the third silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less.
38. A semiconductor device comprising:
a first-conductive type first silicon pillar:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric;
a second silicon pillar underneath the first silicon pillar; and
a third silicon pillar on a top of the first silicon pillar,
the third silicon pillar includes a second-conductive type high-concentration impurity region therein,
wherein the second silicon pillar includes a second-conductive type high-concentration impurity region in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region of the second silicon pillar,
wherein the first-conductive type impurity region of the second silicon pillar has a length which is short enough with respect to a distance between an adjacent two of a plurality of the semiconductor devices on a silicon substrate to enable the second-conductive type high-concentration impurity region of the third silicon pillar and the second-conductive type high-concentration impurity region of the second silicon pillar to comprise injected ions, and
wherein
tan
\ue8a0
(
\u03c0
36
)
\xb7
Tspace
–
(
Lg
+
Ljs
+
Ljd
)
>
Ld
,
, where Tspace is the distance between the adjacent semiconductor devices;
Lg is a length of the gate;
Ljd is a height of the second-conductive type high-concentration impurity region in the second silicon pillar to serve as a drain;
Ljs is a depth of the second-conductive type high-concentration impurity region in the third silicon pillar to serve as a source; and
Ld is a length of the first-conductive type impurity region of the second silicon pillar,
wherein the first silicon pillar comprises a high resistance region or a first-conductive type impurity region, and wherein:
the first-conductive type impurity region of the second silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less; and
the first-conductive type impurity region of the third silicon pillar comprises a second-conductive type impurity region including a region having an impurity concentration of 1E18cm\u22123 or less.
39. The semiconductor device as defined in claim 33, wherein each of the second-conductive type impurity region of the second silicon pillar and the second-conductive type impurity region of the third silicon pillar has a diameter greater than that of the first silicon pillar.
40-41. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Method to route a packet switched mode call (PS) from a first terminal (T1) of a first user (A) who desires to communicate with a second user (B), to a second terminal (T2) of said second user (B) in a multi media telecommunication network, said method comprises a step of
registering said second user (B) via said second terminal (T2) according to a bearer level of said telecommunication network thereby providing bearer level location information (GPRS-LOC-B) of said second user (B) being stored in a bearer level location register (HLR) of said telecommunication network, characterized in that in the event when said second user (B) is not registered for call control on an application level of said telecommunication network said method comprises the steps of:
a) upon reception of said packet switched mode call for said second user (B) retrieving by a call service means (CSM) of said telecommunication network, said bearer level location information (GPRS-LOC-B) of said second user (B) from said bearer level location register (HLR); and
b) transmitting by said call service means (CSM) an alerting message (ALT), on said bearer level, according to said bearer level location information (GPRS-LOC-B) to said second terminal (T2) of said second user (B) and thereby alerting said second terminal (T2) of an incoming packet switched mode call (PS) order to enable thereby said second terminal (T2) to initialize, upon reception of said alerting message (ALT), an application register message (REG) for call control on said application level whereby application level location information (SIP-LOC-B) is provided for storage in an application level location register (HPD) of said telecommunication network and in order to enable thereby said telecommunication network to route said packet switched mode call (PS) to said second terminal (T2) of said second user (B) on said Application level according to said application level location information (SIP-LOC-B):
2. The method according to claim 1, characterized in that said method further comprises a step c) of initializing, upon reception of said alerting message (ALT) by said second terminal (T2), an application register message (REG) for call control on said application level and thereby providing application level location information (SIP-LOC-B) for storage in an application level location register (HPD) of said telecommunication network in order to enable thereby said telecommunication network to route said packet switched mode call to said second terminal (T2) of said second user (B) on said application level.
3. The method to route a packet switched mode call according to any previous claim, characterized in that said telecommunication network is a mobile telecommunication network.
4. The method to route a packet switched mode call according to any previous claim, characterized in that said bearer level of said telecommunication network is a Generic Packet Radio System.
5. The method to route a packet switched mode call according to any previous claim, characterized in that said call control on application level of said telecommunication network is a Session Initiation Protocol whereby said application register message (REG) is a Session Initiation Protocol register message.
6. A method to route a packet switched mode call, characterized in that said method comprises checking a service preference data base of said multi media telecommunication network upon an actual preferred routing mode of said second user (B), and in the event when said actual preferred routing mode is a packet switched routing mode, executing the method to route a packet switched mode call according to any previous claim.
7. The method to route a packet switched mode call according to any one of claim 2 to claim 6, characterized in that said step c) of initializing by said second terminal (T2), an application register message (REG) being executed automatically upon reception of said alerting message (ALT).
8. The method to route a packet switched mode call according to any one of claim 2 to claim 6, characterized in that said method further comprises upon reception of said alerting message (ALT) by said second terminal (T2), signaling to said second user (B) by said second terminal (T2) of reception of said alerting message (ALT); and instructing by said second user (B) to said second terminal (T2) of execution of said step c).
9. A call service means (CSM) multi media telecommunication network to route a packet switched mode call (PS) from a first terminal (T1) of a first user (A) who desires to communicate with a second user (B), to a second terminal (T2) of said second user (B), said second user (B) being registered via said second terminal (T2) according to a bearer level of said telecommunication network whereby bearer level location information (GPRS-LOC-B) of said second user (B) is provided and stored in a bearer level location register (HLR) of said telecommunication network, characterized in that said call service means (CSM) comprises retrieving means (RET) to retrieve, in the event when said second user (B) is not registered for call control on an application level of said telecommunication network, upon reception of said packet switched mode call (PS) for said second user (B), said bearer level location information (GPRSLOC-B) of said second user (B) from said bearer level location register (HLR) being coupled thereto; and transmitting means (TR) to transmit an alerting message (ALT), on said bearer level, according to said bearer level location information (GPRS-LOC-B) to said second terminal (T2) of said second user (B) in order to thereby alert said second terminal (T2) of an incoming packet switched mode call (PS) and to enable thereby said second terminal (T2) to initialize, upon reception of said alerting message (ALT), an application register message (REG) for call control on said application level whereby application level location information (SIP-LOC-B) is provided for storage in an application level location register (HPD) of said telecommunication network and whereby said telecommunication network is enabled to route said packet switched mode call (PS) to said second terminal (T2) of said second user (B) on said application level according to said application level location information (SIP-LOC-B).
10. A second terminal (T2) of a second user (B) in a multi media telecommunication, said second user (B) being registered via said second terminal (T2) according to a bearer level location information (GPRS-LOC-B) of said second user (B) that is stored in a bearer level location register (HLR) of said telecommunication network, a packet switched mode call (PS) needs to be routed from a first terminal (T1) of a first user (A) who desires to communicate with said second user (B), characterized in that said second terminal (T2) comprises receiving means (REC) to receive, in the event when said second user (B) is not registered for call control on an application level of said telecommunication network, an alerting message (ALT) in order to be alerted of an incoming packet switched mode call (PS), said alerting message (ALT) being transmitted by a call service means (CSM) of said telecommunication network to said second terminal (T2) of said second user (B) on said bearer level according to said bearer level location information (GPRS-LOC-B), said bearer level location information (GPRS-LOC-B) being retrieved by said call service means (CSM) upon reception of said packet switched mode call for said second user (B) from said bearer level location register (HLR) accordingly, said second terminal (T2) being thereby enabled to initialize an application register message (REG) for call control on said application level whereby application level location information (SIP-LOC-B) is provided for storage in an application level location register (HPD) of said telecommunication network and in order to enable thereby said telecommunication network to route said packet switched mode call (PS) to said second terminal (T2) of said second user (B) on said application level according to said application level location information (SIPLOC-B).
11. The second terminal (T2) according to claim 10, characterized in that it further comprises initializing means (INIT) to initialize said application register message (REG) for call control on said application level.
12. A multi media telecommunication network, characterized in that said network comprises any one of a call service means (CSM) according to claim 9, a second terminal (T2) according to claim 10 and a second terminal (T2) according to claim 11.