1. A vehicular electronic control apparatus comprising:
a mother unit including a microcomputer;
a plurality of ECU modules mounted to the mother unit detachably for performing different controls for a vehicle, respectively;
an operation data communication section for communicating operation data, which the plurality of ECU modules uses in performing operation processing for the respective controls, with the microcomputer;
an alternative operation processing section for causing the communication section to transmit the operation data to at least one of the microcomputer and one ECU module of the plurality of ECU modules through the microcomputer, and for causing the microcomputer or the one ECU module, to which the operation data is transmitted, to perform alternative operation processing corresponding to at least a part of operation processing, which is to be executed by another ECU module of the plurality of ECU modules; and
an ECU load check section configured to check whether each of the plurality of ECU modules is in a high processing load state,
wherein the alternative operation processing section is configured to determine the another ECU module to be an ECU module, which is determined to be in the high processing load state, so that the alternative operation processing is performed by the at least one of the microcomputer and one ECU module in place of the ECU module determined to be in the high processing load state.
2. The vehicular electronic control apparatus according to claim 1, wherein:
the plurality of ECU modules except for at least a predetermined ECU module include respective processing sections for executing the operation processing; and
the alternative operation processing is the part of operation processing, which is to be executed by the another ECU module.
3. The vehicular electronic control apparatus according to claim 1, further comprising:
an operation check section configured to check whether each of the plurality of ECU modules is operating normally;
a processing stop section configured to stop the ECU module, which is determined to be failing to operate normally, from executing the operation processing; and
a notification section configured to provide a notification in the vehicle that the ECU module is failing to operate normally,
wherein the alternative operation processing is a part of the operation processing, which is to be executed by the ECU module determined to be failing to operate normally and to correspond to the another ECU module.
4. The vehicular electronic control apparatus according to claim 3, further comprising:
a backup operation processing section configured to cause at least one of the microcomputer and the one ECU module to execute operation processing for safety travel of the vehicle, when the ECU module for performing a safety control is determined to be failing to operate normally.
5. The vehicular electronic control apparatus according to claim 1, further comprising:
a park check section configured to check whether the vehicle is being parked;
an ECU stop section configured to stop at least one of the plurality of ECU modules from operating, when the vehicle is determined to be being parked; and
a park-time alternative control section configured to cause at least one of the microcomputer and the one ECU module, which is other than the stopped ECU module, from performing a control, which is to be performed by the stopped ECU module while the vehicle is being parked, the stopped ECU module being corresponding to the another ECU module.
6. The vehicular electronic control apparatus according to claim 1, further comprising:
a data format conversion section configured to convert a data format of the operation data outputted from the another ECU module to a data format which is usable by the at least one of the microcomputer and the one ECU module, which executes the alternative operation processing.
7. The vehicular electronic control apparatus according to claim 1, wherein:
the microcomputer receives, as the operation data, a control program required to execute the part of operation processing from the another ECU module, and transmits the control program to the one ECU module so that the alternative operation processing is performed by the one ECU module according to the control program.
8. A vehicular electronic control apparatus comprising:
a mother unit including a microcomputer;
a plurality of ECU modules mounted to the mother unit detachably for performing different controls for a vehicle, respectively;
an operation data communication section for communicating operation data, which the plurality of ECU modules uses in performing operation processing for the respective controls, with the microcomputer;
an alternative operation processing section for causing the communication section to transmit the operation data to at least one of the microcomputer and one ECU module of the plurality of ECU modules through the microcomputer, and for causing the microcomputer or the one ECU module, to which the operation data is transmitted, to perform alternative operation processing corresponding to at least a part of operation processing, which is to be executed by another ECU module of the plurality of ECU modules;
an operation check section configured to check whether each of the plurality of ECU modules is operating normally;
a processing stop section configured to stop the ECU module, which is determined to be failing to operate normally, from executing the operation processing; and
a notification section configured to provide a notification in the vehicle that the ECU module is failing to operate normally,
wherein the alternative operation processing is a part of the operation processing, which is to be executed by the ECU module determined to be failing to operate normally and to correspond to the another ECU module.
9. A vehicular electronic control apparatus comprising:
a mother unit including a microcomputer;
a plurality of ECU modules mounted to the mother unit detachably for performing different controls for a vehicle, respectively;
an operation data communication section for communicating operation data, which the plurality of ECU modules uses in performing operation processing for the respective controls, with the microcomputer;
an alternative operation processing section for causing the communication section to transmit the operation data to at least one of the microcomputer and one ECU module of the plurality of ECU modules through the microcomputer, and for causing the microcomputer or the one ECU module, to which the operation data is transmitted, to perform alternative operation processing corresponding to at least a part of operation processing, which is to be executed by another ECU module of the plurality of ECU modules;
a park check section configured to check whether the vehicle is being parked;
an ECU stop section configured to stop at least one of the plurality of ECU modules from operating, when the vehicle is determined to be being parked; and
a park-time alternative control section configured to cause at least one of the microcomputer and the one ECU module, which is other than the stopped ECU module, from performing a control, which is to be performed by the stopped ECU module while the vehicle is being parked, the stopped ECU module being corresponding to the another ECU module.
10. A vehicular electronic control apparatus comprising:
a mother unit including a microcomputer;
a plurality of ECU modules mounted to the mother unit detachably for performing different controls for a vehicle, respectively;
an operation data communication section for communicating operation data, which the plurality of ECU modules uses in performing operation processing for the respective controls, with the microcomputer;
an alternative operation processing section for causing the communication section to transmit the operation data to at least one of the microcomputer and one ECU module of the plurality of ECU modules through the microcomputer, and for causing the microcomputer or the one ECU module, to which the operation data is transmitted, to perform alternative operation processing corresponding to at least a part of operation processing, which is to be executed by another ECU module of the plurality of ECU modules; and
a data format conversion section configured to convert a data format of the operation data outputted from the another ECU module to a data format which is usable by the at least one of the microcomputer and the one ECU module, which executes the alternative operation processing.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for verifying an array cell of a memory device comprising:
determining after an erase pulse or a program pulse a threshold of an array cell addressed through a selected word-line and a selected bit-line by applying an identical voltage ramp to the selected word-line and to a control gate of a reference cell while biasing at a bias voltage deselected word-lines through distribution lines of a voltage generated by a charge pump generator; and
temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.
2. The method of claim 1 wherein determining follows a applying a soft program pulse for recovering the array cell from a depleted condition and the bias voltage of deselected word-lines is of a sign and value sufficient to ensure turn off of any cell still depleted and that is coupled to the selected bit-line.
3. The method of claim 1 wherein the temporary decoupling is made by placing in a high impedance state the distribution line of the bias voltage to respective drivers of the deselected word-lines.
4. The method of claim 1 wherein the temporary decoupling is made by commanding stopping of the charge pump generator and by isolating a voltage divider that provides an estimation of a voltage output by said charge pump generator for a regulation loop thereof.
5. The method of claim 1 wherein the memory device comprises a multi-level two-bitscell FLASH-EPROM device.
6. A method for verifying an array cell of a memory device comprising:
determining after an erase pulse or program pulse a threshold of an array cell addressed through a selected word-line and a selected bit-line by applying a corresponding voltage ramp to the selected word-line and to a control gate of a reference cell while biasing deselected word-lines through distribution lines; and
temporarily decoupling the deselected word-lines from the distribution lines during the voltage ramp.
7. The method of claim 6 wherein determining follows a applying a soft program pulse for recovering the array cell from a depleted condition and a bias voltage of deselected word-lines is of a sign and value sufficient to ensure turn off of any cell still depleted and that is coupled to the selected bit-line.
8. The method of claim 6 wherein the temporary decoupling is made by placing in a high impedance state the distribution line to respective drivers of the deselected word-lines.
9. The method of claim 6 wherein the temporary decoupling is made by commanding stopping of a charge pump generator supplying a bias voltage to the distribution line of the deselected word-lines.
10. The method of claim 9 wherein the temporary decoupling further comprises isolating a voltage divider that provides an estimation of a voltage output by the charge pump generator for a regulation loop thereof.
11. The method of claim 6 wherein the memory device comprises a multi-level two-bitscell FLASH-EPROM device.
12. A memory device comprising:
an array of cells;
word-lines and bit-lines coupled to said cells;
distribution lines coupled to said word-lines;
a reference cell having a control gate; and
a control circuit for verifying a cell by determining after an erase pulse or program pulse a threshold of the cell addressed through a selected word-line and a selected bit-line by applying a corresponding voltage ramp to the selected word-line and to the control gate of the reference cell while biasing deselected word-lines through distribution lines, and temporarily decoupling the deselected array word-lines from the distribution lines during the voltage ramp.
13. The memory device of claim 12 wherein said control circuit applies a soft program pulse for recovering the cell from a depleted condition and a bias voltage of deselected array word-lines is of a sign and value sufficient to ensure turn off of any cell still depleted and that is coupled to the selected bit-line.
14. The memory device of claim 12 further comprising respective drivers for the word-lines; and wherein said control circuit makes the temporary decoupling by placing in a high impedance state the distribution line to respective drivers of the deselected word-lines.
15. The memory device of claim 12 further comprising a charge pump generator for supplying a bias voltage to the distribution line of the deselected word-lines; and wherein said control circuit makes the temporary decoupling by commanding stopping of said charge pump generator supplying the bias voltage to the distribution line of the deselected word-lines.
16. The memory device of claim 15 wherein said charge pump generator further comprises a voltage divider providing an estimation of a voltage output by said charge pump generator as part of a regulation loop; and wherein said control circuit further makes the temporary decoupling by isolating said voltage divider.
17. The memory device of claim 12 wherein said cells comprise multi-level two-bitscells of a FLASH-EPROM type.