1. A pretensioner coupling for a seat belt retractor for a motor vehicle, the retractor having a belt shaft and a pretensioner drive adapted for rotating to wind the belt shaft, the pretensioner coupling comprising:
a coupling latch movably arranged between a release position and an engagement position, the coupling latch producing a load-transmitting rotational connection between the belt shaft and the pretensioner drive when in the engagement position and movable out of the engagement position and into the release position to permit relative rotation between the belt shaft and the pretensioner drive, and
an inertial mass mounted on the belt shaft and being rotationally arranged in relation to the belt shaft, the coupling latch being coupled with the inertial mass wherein the inertial mass rotates more slowly than the pretensioner drive when the pretensioner drive has been activated to wind the belt shaft thereby moving the coupling latch to the engagement position, and the inertial mass rotating faster than the belt shaft at the conclusion of the winding of the belt shaft by the pretensioner drive, moving the coupling latch to the release position, and wherein the coupling latch is arranged to swing between the release position and engagement position, the coupling latch having a pin which engages a radial cam track formed by the inertial mass.
2. The pretensioner coupling according to claim 1, wherein the radial cam is arranged in the inertial mass having a shape that, when the pretensioner drive is activated to wind the belt shaft, the pin of the coupling latch being located in the radial cam track moves the coupling latch into the engagement position, and the pin engages and accelerates the inertial mass in the direction of winding of the belt shaft by the pretensioner drive, and when the rotational speed of the belt shaft slows down, the pin moves in the cam track to move the coupling latch from the engagement position into the release position.
3. The pretensioner coupling according to claim 1 wherein the pretensioner drive includes a drive wheel journalled for rotation on a coupling neck of the belt shaft, the coupling neck forming a notch and the drivewheel forming a recess, the coupling latch engaging both the notch and the recess in the engagement position thereby rotationally coupling the drivewheel and the belt shaft, and in the release position, disengaging the connection between the notch and the recess, allowing relative rotation between the drivewheel and the belt shaft.
4. The pretensioner coupling according to claim 1 wherein the radial cam track is spiral in shape having first and second ends with the first end being located closer to the rotational axis of the belt shaft then the second end.
5. The pretensioner coupling according to claim 4 wherein the pin engages the first end to drive the inertial mass to rotate.
6. A pretensioner coupling for a seat belt retractor for a motor vehicle, the retractor having a belt shaft and a pretensioner drive for winding the belt shaft, the pretensioner coupling comprising:
the belt shaft having a coupling neck forming a notch,
the pretensioner drive having a drivewheel journalled for rotation on the coupling neck, the drivewheel forming a recess,
a coupling latch having an engagement region and a pin positioned on opposite ends of an arm, the latch movable between a release position and an engagement position, the coupling latch engagement region engaging both the notch and the recess producing a load-transmitting rotational connection between the belt shaft and the drivewheel when in the engagement position, and movable out of the engagement position and into the release position wherein the engagement region disengages coupling between the recess and the notch to permit relative rotation between the belt shaft and the drivewheel, and
an inertial mass mounted on the belt shaft and being rotationally arranged in relation to the belt shaft, the inertial mass forming a cam track in the form of a spiral, the pin positioned in the cam track wherein when the pretensioner drive is activated to drive the belt shaft, the drivewheel rotates relative to the inertial mass, moving the pin in the cam track and orienting the engagement region to the engaged position and the pin reaching an end of the cam track forcing the inertial mass to rotate with the belt shaft, and upon the pretensioner drive no longer driving the drivewheel, the inertial mass is rotating faster than the belt shaft causing the pin to move in the cam track to move the latch to the release position.
7. The pretensioner coupling according to claim 6 wherein the radial cam track is spiral in shape having first and second ends with the first end being located closer to the rotational axis of the belt shaft than the second end.
8. The pretensioner coupling according to claim 6 wherein the pin is driven to engage the first end upon driving by the pretensioner drive.
9. The pretensioner coupling according to claim 7 wherein the pin engages the first end to drive the inertial mass to rotate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A control unit for a first-in, first-out (FIFO) buffer for transferring data between a first clock domain corresponding to a first clock signal and a second clock domain corresponding to a second signal, the control unit comprising:
a first clocked storage device clocked by the first clock signal, wherein the first clocked storage device is configured to store a first pointer to address the FIFO buffer;
a second clocked storage device clocked by the second clock signal, wherein the second clocked storage device is configured to store a second pointer to address the FIFO buffer;
a third clocked storage device clocked by the second clock signal, wherein the third clocked storage device is coupled to receive a third pointer that corresponds to the first pointer, the third pointer transmitted from the first clock domain to the second clock domain to be received by the third clocked storage device;
a fourth clocked storage device having an input coupled to an output of the third clocked storage device and clocked by the second clock signal;
a mode control unit configured to select the output of the third clocked storage device to be compared to the second pointer responsive to monitoring a history of samples corresponding to one of the first clock signal or the second clock signal, wherein the mode control unit is configured to select the output of the third clocked storage device if a transition in a value of the third pointer, if any, meets setup and hold requirements of the third clocked storage device according to a phase relationship between the second clock signal and the first clock signal as indicated by the history of samples.
2. The control unit as recited in claim 1 further comprising a clock divider in the second clock domain, wherein the clock divider is configured to generate a third clock signal, wherein a frequency of the second clock signal is an integer multiple of the third clock signal, and wherein the history of samples are samples of the third clock signal.
3. The control unit as recited in claim 2 further comprising a plurality of clocked storage devices, wherein each of the clocked storage devices are triggered by either a rising edge or a falling edge of the first clock signal, and wherein the plurality of clocked storage devices are configured to synchronize the third clock signal to the first clock domain.
4. The control unit as recited in claim 3 wherein the plurality of clocked storage devices comprises a fifth clocked storage device and a sixth clocked storage device coupled in series and triggered by the falling edge of the first clock signal, and wherein the plurality of clocked storage devices comprises a seventh clocked storage device and an eighth clocked storage device coupled in series and triggered by the rising edge of the first clock signal.
5. The control unit as recited in claim 4 wherein the plurality of clocked storage devices further comprises a ninth clocked storage device triggered by the rising edge of the first clock signal and having an input coupled to an output of the sixth clocked storage device, wherein an output of the ninth clocked storage device and an output of the eighth clocked storage device comprises samples to be added to the history of samples.
6. The control unit as recited in claim 5 further comprising a detect circuit configured to maintain the history of samples and configured to detect rising edges of the first clock signal responsive to the history, and wherein the detect circuit is further configured to detect if a run length of the history of samples leading to the detected rising edge is a less likely length of the possible run lengths based on a ratio of a first frequency of the first clock signal and a second frequency of the second clock signal.
7. The control unit as recited in claim 1 further comprising a pointer generator operable in the first clock domain and coupled to the first clocked storage device, wherein the pointer generator is configured to generate the third pointer from the first pointer to be transmitted to the second clock domain, wherein the pointer generator is responsive to one or more control signals to generate the third pointer, and wherein the mode control unit is coupled to the pointer generator and configured to generate the one or more control signals responsive to monitoring the history of samples, wherein the mode control unit is configured to generate the one or more control signals to ensure that transitions in a value of the third pointer occur at times that meet setup and hold requirements in the second clock domain.
8. The control unit as recited in claim 7 wherein the pointer generator comprises a fifth clocked storage device triggered by a rising edge of the first clock signal and a sixth clocked storage device triggered by a falling edge of the first clock signal, wherein the one or more control signals enable one of the fifth clocked storage device and the sixth clocked storage device to capture a transition of the first pointer dependent on which is more likely to propagate the transition to the second clock domain to meet the setup and hold requirements.
9. The control unit as recited in claim 8 wherein the pointer generator further comprises a first bitwise exclusive OR (XOR) circuit having inputs coupled to the outputs of the fifth clocked storage device and the sixth clocked storage device, a second bitwise XOR circuit having inputs coupled to the output of the first bitwise XOR circuit and to receive the first pointer, a third bitwise XOR circuit having inputs coupled to the output of the second bitwise XOR circuit and the output of the fifth clocked storage device and further having an output coupled to the input of the fifth clocked storage device, and a fourth bitwise XOR circuit having inputs coupled to the output of the second bitwise XOR circuit and the output of the sixth clocked storage device and further having an output coupled to the input of the sixth clocked storage device.
10. The control unit as recited in claim 1 wherein the mode control unit is configured to generate a select signal to select the third clocked storage device, wherein the select signal is double synchronized to the second clock domain.
11. The control unit as recited in claim 10 further comprising a fifth clocked storage device and a sixth clocked storage device coupled in series and the input of the fifth clocked storage device is coupled to receive the third pointer, wherein the fifth clocked storage device and the sixth clocked storage device are triggered by the falling edge of the second clock signal.
12. The control unit as recited in claim 11 wherein the select signal selects between the output of the sixth clocked storage device and the output of the third clocked storage device to be compared to the second pointer.
13. The control unit as recited in claim 12 further comprising:
a first comparator coupled to receive the selected output of the third clocked storage device or the sixth clocked storage device and coupled to receive the second pointer, the first comparator configured to generate a first comparison result;
a second comparator coupled to receive the output of the fourth clocked storage device and coupled to receive the second pointer, the second comparator configured to generate a second comparison result; and
a logic gate configured to logically AND the first comparison result and the second comparison result.
14. The control unit as recited in claim 13 wherein the first pointer is a write pointer to write data to the FIFO buffer, the second pointer is a read pointer to read data from the FIFO buffer, and the output of the logic gate is an empty signal indicating that the FIFO buffer is empty.
15. In a first-in, first-out (FIFO) buffer for transferring data between a first clock domain corresponding to a first clock signal and a second clock domain corresponding to a second signal, wherein a first pointer in the first clock domain addresses the FIFO buffer and a second pointer in the second clock domain addresses the FIFO buffer, a method comprising:
monitoring a history of samples corresponding to one of the first clock signal or the second clock signal;
generating a third pointer from the first pointer to be transmitted to the second clock domain, the generating including ensuring that transitions in a value of the third pointer occur at times that meet setup and hold requirements in the second clock domain, the generating responsive to the history of samples; and
capturing the third pointer in the second clock domain and comparing the third pointer to the second pointer.
16. The method as recited in claim 15 further comprising a dividing the second clock signal to generate a third clock signal, wherein a frequency of the second clock signal is an integer multiple of the third clock signal, and wherein the history of samples are samples of the third clock signal.
17. The method as recited in claim 15 further comprising detecting rising edges of the first clock signal responsive to the history of samples, and detecting if a run length of the history of samples leading to the detected rising edge is a less likely length of the possible run lengths based on a ratio of a first frequency of the first clock signal and a second frequency of the second clock signal.
18. The method as recited in claim 15 further comprising double synchronizing the third pointer in the second clock domain, and selecting between the third pointer and the double synchronized third pointer to compare to the second pointer.
19. A control unit for a first-in, first-out (FIFO) buffer for transferring data between a first clock domain corresponding to a first clock signal and a second clock domain corresponding to a second signal, the control unit comprising:
a first clocked storage device clocked by the first clock signal, wherein the first clocked storage device is configured to store a first pointer to address the FIFO buffer;
a second clocked storage device clocked by the second clock signal, wherein the second clocked storage device is configured to store a second pointer to address the FIFO buffer;
a pointer generator operable in the first clock domain and coupled to the first clocked storage device, wherein the pointer generator is configured to generate a third pointer from the first pointer to be transmitted to the second clock domain, wherein the pointer generator is responsive to one or more control signals to generate the third pointer;
a mode control unit coupled to the pointer generator and configured to generate the one or more control signals responsive to monitoring a history of samples corresponding to the second clock signal, wherein the mode control unit is configured to generate the one or more control signals to ensure that transitions in a value of the third pointer occur at times that meet setup and hold requirements in the second clock domain; and
a third clocked storage device clocked by the second clock signal, wherein the third clocked storage device is coupled to receive the third pointer from the pointer generator, and wherein the mode control unit is configured to select an output of the third clocked storage device to be compared to the second pointer.
20. The control unit as recited in claim 19 further comprising a detect circuit configured to maintain the history of samples corresponding to the first clock signal and configured to detect rising edges of the first clock signal responsive to the history, and wherein the detect circuit is further configured to detect if a run length of the history of samples leading to the detected rising edge is a less likely length of the possible run lengths based on a ratio of a first frequency of the first clock signal and a second frequency of the second clock signal.
21. An apparatus comprising:
a first clocked storage device operable in a first clock domain corresponding to a first clock signal, the first clocked storage device having an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal; and
control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device, the control circuitry responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.
22. The apparatus as recited in claim 21 wherein the phase relationship between the first clock signal and the second clock signal varies from clock cycle to clock cycle.