1. A semiconductor memory comprising:
a semiconductor region;
a plurality of floating gate electrodes arranged in a matrix on the semiconductor region through a tunnel insulating layer;
a plurality of inter-gate insulating layers disposed only on the plurality of floating gate electrodes, respectively;
a plurality of control gate electrodes disposed on the plurality of inter-gate insulating layers, respectively; and
a plurality of isolation insulators extending between a plurality of arrangements of the control gate electrodes along a column direction of the matrix, each of the isolation insulators penetrating into the semiconductor region so as to electrically isolate the plurality of inter-gate insulating layers from each other in the column direction.
2. The semiconductor memory of claim 1, further comprising a plurality of wiring portions running along a row direction of the matrix so as to share the control gate electrodes arranged along the row direction, each of the wiring portions electrically connecting the control gate electrodes in the row direction.
3. The semiconductor memory of claim 2, further comprising a plurality of silicide layers disposed on the wiring portions, respectively, each of the silicide layers electrically connected to corresponding one of the wiring portions.
4. The semiconductor memory of claim 3, further comprising a plurality of barrier insulators disposed on the silicide layers, respectively.
5. The semiconductor memory of claim 1, wherein each of the inter-gate insulating layers is composed of silicon dioxide.
6. The semiconductor memory of claim 1, wherein each of the inter-gate insulating layers is composed of silicon nitride.
7. The semiconductor memory of claim 1, wherein each of the inter-gate insulating layers is composed of alumina.
8. The semiconductor memory of claim 1, wherein each of the inter-gate insulating layers is composed of hafnium oxide.
9. The semiconductor memory of claim 1, wherein each of the inter-gate insulating layers is composed of zirconium oxide.
10. The semiconductor memory of claim 1, wherein each of the control gate electrodes is composed of titanium silicide.
11. The semiconductor memory of claim 1, wherein each of the control gate electrodes is composed of cobalt silicide.
12. The semiconductor memory of claim 1, wherein each of the control gate electrodes is composed of nickel silicide.
13. A method for manufacturing a semiconductor memory including:
forming a tunnel insulating layer on a semiconductor region;
depositing a first conducting layer on the tunnel insulating layer;
forming an interlayer insulator on the first conducting layer;
depositing a second conducting layer on the interlayer insulator;
delineating a plurality of column isolation trenches penetrating from the second conducting layer to an interior of the semiconductor region, the column isolation trenches extending in a column direction so as to divide the second conducting layer, the interlayer insulator, and the first conducting layer into a plurality of strips of the second conducting layers, the interlayer insulators, and the first conducting layers, respectively;
filling the plurality of column isolation trenches with a plurality of isolation insulators so that the plurality of strips of the interlayer insulators are isolated from each other in the column direction by the plurality of isolation insulators; and
dividing the stripes of the first conducting layers, the interlayer insulators, and the second conducting layers by a plurality of row isolation trenches running along a row direction perpendicular to the column direction to form a plurality of floating gate electrodes on the tunnel insulating layer, a plurality of inter-gate insulating layers on the plurality of floating gate electrodes, and a plurality of control gate electrodes on the plurality of inter-gate insulating layers, respectively.
14. The method of claim 13, further including:
forming a plurality of wiring portions extending in the row direction on the second conducting layer before dividing the strips of the first conducting layers, the interlayer insulators, and the second conducting layers.
15. The method of claim 14, further including:
depositing a silicide layer on the wiring portion.
16. The method of claim 13, wherein each of the inter-gate insulating layers is composed of silicon dioxide.
17. The method of claim 13, wherein each of the inter-gate insulating layers is composed of silicon nitride.
18. The method of claim 13, wherein each of the inter-gate insulating layers is composed of alumina.
19. The method of claim 13, wherein each of the inter-gate insulating layers is composed of hafnium oxide.
20. The method of claim 13, wherein each of the inter-gate insulating layers is composed of zirconium oxide.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An antenna apparatus comprising:
a first earth plate; and
a radio frequency circuit board in which (i) at least one radio frequency communication circuit that communicates a communication signal on radio waves and (ii) a second earth plate are formed,
the radio frequency communication circuit including at least one of (i) a radio frequency transmission circuit that transmits a transmission signal as the communication signal and (ii) a radio frequency reception circuit that receives a reception signal as the communication signal,
the second earth plate serving as a grounding electric potential of the radio frequency communication circuit,
the radio frequency circuit board being arranged such that a plate plane of the second earth plate intersects with a plate plane of the first earth plate,
wherein:
the first earth plate and the second earth plate are in electrical insulation state at least with respect to signals of frequencies of the communication signal; and
a feed of the communication signal by the radio frequency communication circuit is executed by an unbalanced feed for each of the radio frequency communication circuit, while for the each of the radio frequency communication circuit, a feed line in the unbalanced feed is connected with the first earth plate and a ground line in the unbalanced feed is connected with the second earth plate.
2. The antenna apparatus according to claim 1, wherein:
the radio frequency circuit board includes a plurality of the radio frequency communication circuits;
for each of the radio frequency communication circuits, a feed point is provided as a connection point between the feed line and the first earth plate, whereas a ground connection point is provided as a connection point between the ground line and the second earth plate; and
the feed points of the plurality of the radio frequency communication circuits are arranged in a direction that is parallel with the plate plane of the first earth plate and parallel with the plate plane of the second earth plate while being separated from each other in a horizontal direction of the plate plane of the second earth plate, and, similarly, the ground connection points of the plurality of the radio frequency communication circuits are arranged in a direction that is parallel with the plate plane of the first earth plate and parallel with the plate plane of the second earth plate while being separated from each other in a horizontal direction of the plate plane of the second earth plate.
3. The antenna apparatus according to claim 2, wherein:
the radio frequency circuit board include at least two radio frequency communication circuits;
one of the two ground connection points of the two radio frequency communication circuits is arranged in a predetermined first end region which contains one end of both ends in the horizontal direction of the radio frequency circuit board; and
an other of the two ground connection points is arranged in a predetermined second end region that contains an other end of the both ends in the horizontal direction of the radio frequency circuit board.
4. The antenna apparatus according to claim 1,
wherein the radio frequency circuit board is connected with an external power line for supplying an operating power of the radio frequency communication circuit from an external instrument, and an external ground line that is connected with a ground of the external instrument,
the antenna further comprising:
an impedance component connected in series with the external ground line in order to achieve the electrical insulation state,
the impedance component providing
an impedance to a signal of a frequency of the communication signal as being equal to or greater than a predetermined high impedance value and
an impedance to direct current as being smaller than a predetermined low impedance value that is less than the predetermined high impedance value.
5. The antenna apparatus according to claim 1, wherein:
the radio frequency circuit board is connected with an external power line, an external ground line, and an external signal line,
the external power line being for supplying an operating power of the radio frequency communication circuit from an external instrument,
the external ground line being connected with a ground of the external instrument,
the external signal line communicating data with the external instrument; and
an impedance component is provided in each of the external ground line, the external power line, and the external signal line.
6. The antenna apparatus according to claim 1, wherein:
the radio frequency circuit board is connected with an external power line, an external ground line, and an external signal line,
the external power line being for supplying an operating power of the radio frequency communication circuit from an external instrument,
the external ground line being connected with a ground of the external instrument,
the external signal line communicating data with the external instrument; and
a bypass capacitor is connected in between the external power line and the external ground line, whereas a bypass capacitor is connected in between the external ground line and the external signal line.