1-21. (canceled)
22. A tracking system comprising:
an internal device configured for moving in an internal tract of the body, the internal device comprising an acoustic receiver and an acoustic transmitter,
an external apparatus comprising an acoustic transmitter and a plurality of acoustic receivers,
an external controller for directing transmission of incident acoustic signals by the transmitter of the external apparatus and for monitoring detection of acoustic responses by the receivers,
an internal controller for monitoring detection of said incident signals by the receiver of the internal device and for directing transmission of said acoustic responses by the transmitter of the internal device, and
a data processor for determining time-of-flight data for the acoustic signals, and for generating location data for the internal device according to said time-of-flight data.
23. The tracking system as claimed in claim 22, wherein the internal device controller directs transmission of the response after a pre-set delay from detection of the transmission, whereby the response is a simulated echo.
24. The tracking system as claimed in claim 22, wherein the internal device is a capsule configured for movement in an internal tract.
25. The tracking system as claimed in claim 22, wherein the external apparatus transmitter comprises a piezoelectric crystal.
26. The tracking system as claimed in claim 22, wherein the internal device transmitter and receiver comprise a surface acoustic wave transducer performing both transmitter and receiver functions.
27. The tracking system as claimed in claim 22, wherein the internal device transmitter generates the response signal with a pulse train of frequency different to that of a pulse train of said incident signal.
28. The tracking system as claimed in claim 22, wherein the controllers ignore signals received within a time period after a first signal of a measuring point in order to eliminate reflected signals.
29. The tracking system as claimed in claim 28, wherein the controllers change state to a sleep mode within said time period.
30. The tracking system as claimed in claim 22, wherein the processor determines differences between times-of-flight between the internal device and the receivers and processes said data to perform the tracking computations.
31. The tracking system as claimed in claim 22, wherein the external apparatus comprises a belt supporting the receivers at locations chosen to minimise interference in paths between the internal device and the receivers when the belt is worn around the patient’s torso.
32. The tracking system as claimed in claim 22, whereby the belt is configured to be worn and the transmitters and the receivers operate in a non-invasive manner whereby the tracking system operates in a procedure which is ambulatory.
33. The tracking system as claimed in claim 31, wherein the receivers are located on the belt so that patient bone interference in the path is minimised when the belt is worn around the patient’s torso.
34. The tracking system as claimed in claim 22, wherein the data processor computes internal device location by re-computing a length variable at time intervals in a successive accumulation method.
35. The tracking system as claimed in claim 34, wherein the variable is initialised at a reference position in a reference volume and is re-computed only while the location is with in said reference volume.
36. The tracking system as claimed in claim 34, wherein the variable is initialised at a reference position in a reference volume and is re-computed only while the location is with in said reference volume wherein the reference volume is cylindrical.
37. The tracking system as claimed in claim 22, wherein the data processor compensates for organ densities in the paths between the internal device and the external apparatus receivers.
paths between the internal device and the external apparatus receivers.
38. The tracking system as claimed in claim 22, wherein retrograde peristalsis is accommodated by the processor.
39. The tracking system as claimed in claim 22, wherein the internal device comprises a capsule configured for movement in an internal tract, and the capsule comprises a sensor for internal investigation.
40. The tracking system as claimed in claim 39, wherein the capsule comprises a pressure sensor for measuring internal tract pressure.
41. The tracking system as claimed in claim 22, wherein the internal device comprises a casing which facilitates acoustic transmission and reception compatible with human organs.
42. The tracking system as claimed in claim 39, wherein the internal device comprises a casing which operates as an RF transmitter for a sensor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nonvolatile semiconductor memory device comprising:
a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells, a first select gate transistor and a second select gate transistor, the plurality of memory cells being connected in series, the plurality of memory cells being connected between a source of the first select gate transistor and a drain of the second select gate transistor;
a first source line located along a first direction in the memory cell array, the first source line being connected to a source of the second select gate transistor, the first source line being consisted of a first conductive layer;
a word line located along the first direction, a gate electrode of one of the plurality of memory cells being connected to the word line, the word line being consisted of a second conductive layer;
a bit line located along a second direction perpendicular to the first direction, the bit line being connected to a drain of the first select gate transistor, the bit line being consisted of a third conductive layer; and
wherein the first conductive layer is located above the second conductive layer and the first conductive layer is located below the third conductive layer.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the source of the second select gate transistor is connected to the first source line through a first interconnection layer.
3. The nonvolatile semiconductor memory device according to claim 1, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of the third conductive layer.
4. The nonvolatile semiconductor memory device according to claim 1, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
5. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first bit line;
a first word line;
a first memory cell unit connected to both the first bit line and the first word line;
a second memory cell unit connected to the first bit line, the second memory cell unit being not connected to the first word line;
a third memory cell unit connected to the first word line, the third memory cell unit being not connected to the first bit line,
wherein the source of the second select gate transistor included in the first memory cell unit, the source of the second select gate transistor included in the second memory cell unit, and the source of the second select gate transistor included in the third memory cell unit are connected to the same first source line in the memory cell array.
6. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a second source line located along the second direction in the memory cell array, the second source line being consisted of a conductive layer located above the first conductive layer;
wherein the second source line is connected to the first source line in the memory cell array.
7. The nonvolatile semiconductor memory device according to claim 6, wherein the second source line is consisted of the third conductive layer.
8. The nonvolatile semiconductor memory device according to claim 6, wherein the second source line is consisted of a conductive layer located above the third conductive layer.
9. The nonvolatile semiconductor memory device according to claim 6, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
10. The nonvolatile semiconductor memory device according to claim 6, wherein a sheet resistance of the third conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
11. The nonvolatile semiconductor memory device according to claim 6, wherein there are a plurality of the second source lines in the memory cell array, and each of the plurality of the second source lines is connected to a plurality of the first source lines in the memory cell array.
12. The nonvolatile semiconductor memory device according to claim 6, wherein the second source line and the first source line are connected to each other in a shunt area.
13. The nonvolatile semiconductor memory device according to claim 6, wherein there are a plurality of the first source lines in the memory cell array, and each of the plurality of the first source lines is connected to a plurality of the second source lines in the memory cell array.
14. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first memory cell unit connected to the first source line; and
a first word line connected to the first memory cell unit,
wherein the first source line is located over the first word line.
15. The nonvolatile semiconductor memory device according to claim 14, wherein the first word line is closest to the second select gate transistor included in the first memory cell unit.
16. The nonvolatile semiconductor memory device according to claim 1, wherein a width of the first source line is larger than a width of the word line.
17. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first memory cell unit connected to the first source line;
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein the first source line is located over the second select gate line connected to the first memory cell unit.
18. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein a width of the first source line is larger than both a width of the first select gate line and a width of the second select gate line.
19. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line;
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line; and
a first select gate bypass line which is provided along the first direction in the memory cell array, the first select gate bypass line being connected to the first select gate line, the first select gate bypass line being located above both the first select gate line and the word line, the first select gate bypass line being consisted of the first conductive layer.
20. The nonvolatile semiconductor memory device according to claim 19, wherein a width of the first select gate bypass line is larger than both a width of the first select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the first select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the first select gate bypass line is located over the word line, and the first select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.
21. The nonvolatile semiconductor memory device according to claim 19, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
22. The nonvolatile semiconductor memory device according to claim 19, further comprising:
a second select gate bypass line which is provided along the first direction in the memory cell array, the second select gate bypass line being connected to the second select gate line, the second select gate bypass line being located above any of the first select gate line, the second select gate line and the word line, the second select gate bypass line being consisted of the first conductive layer,
wherein a width of the second select gate bypass line is larger than both a width of the second select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the second select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the second select gate bypass line is located over the word line, and the second select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.
23. A nonvolatile semiconductor memory device comprising:
a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells, a first select gate transistor and a second select gate transistor, the plurality of memory cells being connected in series, the plurality of memory cells being connected between a source of the first select gate transistor and a drain of the second select gate transistor;
a source line connected to a source of the second select gate transistor;
a first source line which is at least a portion of the source line, the first source line located along a first direction in the memory cell array, the first source line being consisted of a first conductive layer;
a word line located along the first direction, a gate electrode of one of the plurality of memory cells being connected to the word line, the word line being consisted of a second conductive layer;
a bit line located along a second direction perpendicular to the first direction, the bit line being connected to a drain of the first select gate transistor, the bit line being consisted of a third conductive layer; and
wherein the first conductive layer is located above the second conductive layer and the first conductive layer is located below the third conductive layer.
24. The nonvolatile semiconductor memory device according to claim 23, wherein the source of the second select gate transistor is connected to the first source line through a first interconnection layer.
25. The nonvolatile semiconductor memory device according to claim 23, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of the third conductive layer.
26. The nonvolatile semiconductor memory device according to claim 23, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
27. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first bit line;
a first word line;
a first memory cell unit connected to both the first bit line and the first word line;
a second memory cell unit connected to the first bit line, the second memory cell unit being not connected to the first word line;
a third memory cell unit connected to the first word line, the third memory cell unit being not connected to the first bit line,
wherein the source of the second select gate transistor included in the first memory cell unit, the source of the second select gate transistor included in the second memory cell unit, and the source of the second select gate transistor included in the third memory cell unit are connected to the same first source line in the memory cell array.
28. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a second source line which is at least a portion of the source line, the second source line located along the second direction in the memory cell array, the second source line being consisted of a conductive layer located above the first conductive layer;
wherein the second source line is connected to the first source line in the memory cell array.
29. The nonvolatile semiconductor memory device according to claim 28, wherein the second source line is consisted of the third conductive layer.
30. The nonvolatile semiconductor memory device according to claim 28, wherein the second source line is consisted of a conductive layer located above the third conductive layer.
31. The nonvolatile semiconductor memory device according to claim 28, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
32. The nonvolatile semiconductor memory device according to claim 28, wherein a sheet resistance of the third conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
33. The nonvolatile semiconductor memory device according to claim 28, wherein the second source line and the first source line are connected to each other in a shunt area.
34. The nonvolatile semiconductor memory device according to claim 28, wherein there are a plurality of the second source lines in the memory cell array, and each of the plurality of the second source lines is connected to a plurality of the first source lines in the memory cell array.
35. The nonvolatile semiconductor memory device according to claim 28, wherein there are a plurality of the first source lines in the memory cell array, and each of the plurality of the first source lines is connected to a plurality of the second source lines in the memory cell array.
36. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first memory cell unit connected to the first source line; and
a first word line connected to the first memory cell unit,
wherein the first source line is located over the first word line.
37. The nonvolatile semiconductor memory device according to claim 36, wherein the first word line is closest to the second select gate transistor included in the first memory cell unit.
38. The nonvolatile semiconductor memory device according to claim 23, wherein a width of the first source line is larger than a width of the word line.
39. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first memory cell unit connected to the first source line;
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein the first source line is located over the second select gate line connected to the first memory cell unit.
40. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein a width of the first source line is larger than both a width of the first select gate line and a width of the second select gate line.
41. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line;
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line; and
a first select gate bypass line which is provided along the first direction in the memory cell array, the first select gate bypass line being connected to the first select gate line, the first select gate bypass line being located above both the first select gate line and the word line, the first select gate bypass line being consisted of the first conductive layer.
42. The nonvolatile semiconductor memory device according to claim 41, wherein a width of the first select gate bypass line is larger than both a width of the first select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the first select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the first select gate bypass line is located over the word line, and the first select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.
43. The nonvolatile semiconductor memory device according to claim 41, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
44. The nonvolatile semiconductor memory device according to claim 41, further comprising:
a second select gate bypass line which is provided along the first direction in the memory cell array, the second select gate bypass line being connected to the second select gate line, the second select gate bypass line being located above any of the first select gate line, the second select gate line and the word line, the second select gate bypass line being consisted of the first conductive layer,
wherein a width of the second select gate bypass line is larger than both a width of the second select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the second select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the second select gate bypass line is located over the word line, and the second select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.