1. A fault current limiter module in the insulation region of a cryogenic cooling system having at least one fault current limiter set, the apparatus comprising:
a first corona shield disposed along the top portion of said at least one fault current limiter set and electrically coupled to said at least one fault current limiter set;
a second corona shield disposed along the bottom portion of said at least one fault current limiter set and electrically coupled to said at least one fault current limiter set;
wherein said first corona shield and said second corona shield act together to reduce the electric field surrounding said at least one fault current limiter set when voltage is applied to said at least one fault current limiter set.
2. The fault current limiter module, as recited in claim 1, wherein said first corona sheild has a surface area that extends beyond the area defined by the ends of all fault current limiters within said module.
3. The fault current limiter module, as recited in claim 1, wherein said fault current limiter comprises a superconducing element electrically coupled in parallel with a shunt coil.
4. The fault current limiter module, as recited in claim 3, wherein said fault current limiter further comprises a trigger coil electrically coupled in parallel with said superconducting element.
5. The fault current limiter module, as recited in claim 1, wherein the fault current limiter module is disposed within a cryogenic liquid bath.
6. A high voltage fault current limiter system comprising:
at least one fault current limiter module comprising at least one corona shield disposed along the top portion and bottom of said at least one fault current limiter set and electrically coupled to said at least one fault current limiter set and an insulation barrier disposed along at least one side of said at least one fault current limiter set, wherein said at least one corona shield acts to reduce the electric field surrounding said at least one fault current limiter set when voltage is applied to said at least one fault current limiter module.
7. The high voltage fault current limiter system, as recited in claim 6, wherein a bottom corona sheild is coupled to adjacent fault current limiter modules disposed along the bottom of the cryogenic cooling system and is electrically coupled in series between two fault current limiter modules.
8. The high voltage fault current limiter system, as recited in claim 6, wherein said bottom corona shield has a surface area that is nearly equal and alternatively extends beyond the area defined by the ends of all the adjacent fault current limiter modules disposed along the bottom of the high voltage fault current limiter system.
9. The high voltage fault current limiter system, as recited in claim 6, wherein said at least one fault current limiter comprises a superconducing element electrically coupled in parallel with a shunt coil.
10. The high voltage fault current limiter system, as recited in claim 9, wherein said fault current limiter further comprises a trigger coil electrically coupled in parallel with said superconducting element.
11. A high temperature superconductor module in the insulation region of a cryogenic cooling system having at least one HTS device, the apparatus comprising:
a first corona shield disposed along the top portion of said at least one HTS device and electrically coupled to said at least one HTS device;
a second corona shield disposed along the bottom portion of said at least one HTS device and electrically coupled to said at least one HTS device; and
an insulation barrier disposed within the insulation region along at least one side of said at least one HTS device;
wherein said first corona shield and said second corona shield act together to reduce the electric field surrounding said at least one HTS device when voltage is applied to said at least one HTS device.
12. The fault current limiter module, as recited in claim 11, wherein said at least one HTS device is disposed within a cryogenic liquid bath.
13. A high temperature superconductor module, in the insulation region of a cryogenic cooling system having at least one HTS device, the apparatus comprising:
a first corona shield disposed along the top portion of said at least one HTS device and electrically coupled to said at least one HTS device;
a second corona shield disposed along the bottom portion of to at least one HTS device and electrically coupled to said at least one HTS device; and
an insulation barrier disposed within the insulation region along at least one side of said at least one HTS device;
wherein said first corona sheild has a surface area that is nearly equal and alternatively extends beyond the area defined by the ends of all HTS devices within said high temperature superconductor module.
14. The fault current limiter module, as recited in claim 13, wherein said at least one HTS device is disposed within a cryogenic liquid bath.
15. A high voltage fault current limiter system comprising:
at least one fault current limiter module comprising at least one corona shield disposed along the top set portion and bottom of said at least one fault current limiter set and electrically coupled to said at least one fault current limiter set and an insulation barrier disposed along at least one side of said at least one fault current limiter set, wherein said at least one corona shield acts to reduce the electrical field surrounding said at least one fault current limiter set when voltage is applied to said high voltage fault current limiter system;
wherein a bottom corona sheild is coupled to adjacent fault current limiter modules disposed along the bottom of the high voltage current limiter system and wherein said bottom corona shield is electrically coupled in series between two fault current limiter modules.
16. The high voltage fault current limiter system, as recited in claim 15, wherein said bottom corona shield has a surface area that is nearly equal and alternatively extends beyond the area defined by the ends of all the adjacent fault current limiter modules disposed along the bottom of the high temperature fault current limiter system.
17. The high voltage fault current limiter system, as recited in claim 15, wherein said at least one fault current limiter set comprises a superconducing element electrically coupled in parallel with a shunt coil.
18. The high voltage fault current limiter system, as recited in claim 17, wherein said at least one fault current limiter set further comprises a trigger coil electrically coupled in parallel with said superconducting element.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor device comprising:
first and second element formation regions formed to be spaced apart from each other in a main surface of a semiconductor substrate;
a dielectric film formed on the main surface of said semiconductor substrate at a location between said first and second element formation regions;
first electrode patterns being formed above said first and second element formation regions respectively and each having an end portion extended to overlie said dielectric film, said first electrode patterns being formed by patterning of a first electrode layer;
second electrode patterns formed above said first electrode patterns respectively; and
a passivation film formed above said first electrode patterns to be positioned adjacent to said second electrode patterns while covering part of said dielectric film exposed during patterning of said first electrode layer.
2. The semiconductor device according to claim 1, wherein
said first and second element formation regions are structural components of first and second cells respectively,
said first electrode patterns are formed to have a first groove with a first width between the end portions of thereof,
said second electrode patterns are formed to have a second groove with a second width greater than said first width between their end portions to thereby permit partial exposure of upper surfaces of said first electrode patterns, and
said passivation film is formed to bury said first groove and at least part of said second groove.
3. The semiconductor device according to claim 1, wherein
said first and second element formation regions are structural components of first and second cells respectively,
said first electrode patterns are formed to have a first groove with a first width between the end portions thereof,
said second electrode patterns are formed to have a second groove with a second width greater than said first width between their end portions to thereby permit partial exposure of upper surfaces of said first electrode patterns,
said semiconductor device comprises a wiring pattern formed on or above said dielectric film between said first electrode patterns to divide said first groove into a plurality of grooves, and
said passivation film is formed to bury at least part of said second groove and also bury said plurality of grooves of said first groove.
4. The semiconductor device according to claim 1, wherein
the first element formation region is formed at a cell formation portion of a first main surface of said semiconductor substrate,
the second element formation region is formed at a terminate end portion of the first main surface of said semiconductor substrate,
the first and second electrode patterns are prevented from being formed above said second element formation region,
said semiconductor device comprises a third element formation region formed at periphery of said treminate end portion of the first main surface of said semiconductor substrate,
said dielectric film is formed above the first main surface of said semiconductor substrate to permit partial exposure of the first and third element formation regions,
said semiconductor device further comprises a stopper electrode pattern formed above said third element formation region to have its end portion extending to overlie said dielectric film, and a field plate formed above said dielectric film at a location between end portions of said first electrode pattern and said stopper electrode pattern and provided to form a plurality of first grooves together with said first electrode patterns and said stopper electrode pattern,
said second electrode patterns are formed above said first electrode patterns to have their end portions exposed thereabove, and
said passivation film is formed to bury said plurality of first grooves while being formed over at least a portion overlying said first electrode patterns with said second electrode patterns prevented from being formed thereon and over said stopper electrode pattern and also over said field plate.
5. The semiconductor device according to claim 2, wherein said passivation film is formed to bury said first groove and said second groove and to have its end portion formed to extend above said second electrode patterns.
6. The semiconductor device according to claim 3, wherein said first electrode patterns and said wiring pattern are made of the same conductive material.
7. The semiconductor device according to claim 4, wherein said passivation film has one end formed above the second electrode pattern.
8. The semiconductor device according to claim 4, wherein said field plate and said stopper electrode pattern are made of the same conductive material.
9. The semiconductor device according to claim 4, further comprising:
a fourth element formation region formed at a second main surface of said semiconductor substrate; and
a fourth electrode pattern formed above said fourth element formation region.
10. The semiconductor device according to claim 2, wherein said first and second cells comprise:
a gate insulation film formed on or above said semiconductor substrate; and
a gate electrode formed to be in contact with said gate insulation film.
11. The semiconductor device according to claim 1, wherein the first electrode patterns include a barrier metal.
12. The semiconductor device according to claim 11, wherein the second electrode patterns include a metal film.
13. The semiconductor device according to claim 12, wherein said metal film includes at least one of aluminum and copper.
14. The semiconductor device according to claim 1, wherein said passivation film includes a dielectric film formed atop said semiconductor device.
15. The semiconductor device according to claim 1, wherein said passivation film includes a resin.
16. A semiconductor device comprising:
diffusion regions formed in a main surface of a semiconductor substrate;
a dielectric film being formed on or above the main surface of said semiconductor substrate and having contact holes leading to said diffusion regions;
first electrode patterns in contact with said diffusion regions through said contact holes and having end portions extending above said dielectric film;
second electrode patterns formed above said first electrode patterns; and
a passivation film formed directly on said dielectric film and said first electrode patterns.
17. The semiconductor device according to claim 16, wherein said diffusion regions are first and second element formation regions formed at the main surface of said semiconductor substrate to be spared apart from each other.
18. The semiconductor device according to claim 17, wherein
said first and second element formation regions are for use as structural components of first and second cells respectively,
said first electrode patterns are formed to have a first groove with a first width between said end portions,
said second electrode patterns is formed to have a second groove with a second width greater than said first width between their end portions to thereby permit partial exposure of upper surfaces of said first electrode patterns, and
said passivation film is formed to bury said first groove and at least part of said second groove.
19. The semiconductor device according to claim 17, wherein
said first and second element formation regions are structural components of first and second cells respectively,
said first electrode patterns are formed to have a first groove with a first width between the end portions thereof,
said second electrode patterns are formed to have a second groove with a second width greater than said first width between their end portions to thereby cause partial exposure of upper surfaces of said first electrode patterns,
said semiconductor device comprises a wiring pattern formed above said dielectric film at a position between said first electrode patterns while being formed to divide said first groove into a plurality of grooves, and
said passivation film is formed to bury at least part of said second groove and also bury said plurality of grooves of said first groove.
20. The semiconductor device according to claim 17, wherein
the first element formation region is formed at a cell formation portion of a first main surface of said semiconductor substrate,
the second element formation region is formed at a terminate end portion of the first main surface of said semiconductor substrate,
the first and second electrode patterns are prevented from being formed above said second element formation region,
said semiconductor device comprises a third element formation region formed at periphery of the terminate end portion of the first main surface of said semiconductor substrate,
said dielectric film is formed above the first main surface of said semiconductor substrate while permitting partial exposure of the first and third element formation regions,
said semiconductor device further comprises a stopper electrode pattern formed above said third element formation region to have its end portion extending to overlie said dielectric film, and a field plate formed above said dielectric film at a location between end portions of said first electrode patterns and said stopper electrode pattern and provided to form a plurality of first grooves in association with said first electrode patterns and said stopper electrode pattern,
said second electrode patterns are formed above said first electrode patterns to have end portions exposed thereabove, and
said passivation film is formed to bury said plurality of first grooves and formed above at least a portion overlying said first electrode patterns with said second electrode patterns prevented from being formed thereover and above said stopper electrode pattern and also above said field plate.
21. The semiconductor device according to claim 18, wherein said passivation film is formed to bury said first groove and said second groove and has end portions formed to extend onto said second electrode patterns.
22. The semiconductor device according to claim 19, wherein said first electrode patterns and said wiring pattern are made of the same conductive material.
23. The semiconductor device according to claim 20, wherein said passivation film has its one end formed over any one of said second electrode patterns.
24. The semiconductor device according to claim 20, wherein said field plate and said stopper electrode pattern are made of the same conductive material.
25. The semiconductor device according to claim 20, further comprising:
a fourth element formation region formed at a second main surface of said semiconductor substrate; and
a fourth electrode pattern formed above said fourth element formation region.
26. The semiconductor device according to claim 18, wherein said first and second cells comprise:
a gate insulation film formed on or above said semiconductor substrate; and
a gate electrode formed to be in contact with said gate insulation film.
27. The semiconductor device according to claim 16, wherein said first electrode patterns include a barrier metal.
28. The semiconductor device according to claim 27, wherein said second electrode patterns include a metal film.
29. The semiconductor device according to claim 28, wherein said metal film includes at least one of aluminum and copper.
30. The semiconductor device according to claim 16, wherein said passivation film includes a dielectric film formed at an uppermost layer of said semiconductor device.
31. The semiconductor device according to claim 16, wherein said passivation film includes a resin.
32. A semiconductor device comprising:
a semiconductor substrate;
a cell including said semiconductor substrate as its structural component and functioning as at least one of a semiconductor circuit element and a semiconductor switch;
a barrier metal being formed by patterning of a metal layer and becoming a structural component of an electrode pattern of said cell;
a dielectric film placed between said semiconductor substrate and said barrier metal;
a conductive pattern being formed above said barrier metal while being exposed to outside and becoming a structural component of said electrode pattern of said cell; and
a passivation film formed to cover said dielectric film as exposed during patterning of said metal layer and also to locate adjacent to said conductive pattern over said barrier metal.
33. The semiconductor device according to claim 32, wherein
a plurality of cells are provided each of which is similar to said cell,
said dielectric film is placed between said plurality of cells,
a first groove is formed by letting said barrier metal of each of said plurality of cells extend to overlie said dielectric film between said plurality of cells,
due to said conductive pattern of each of said plurality of cells, a second groove greater in width than said first groove is formed on said first groove, and
said passivation film is formed to be buried in the first and second grooves between said plurality of cells.
34. The semiconductor device according to claim 33, further comprising:
a wiring pattern being covered with said passivation film and overlying said dielectric film of said first groove.
35. The semiconductor device according to claim 32, wherein
said semiconductor device has a structure with repeated layout of said plurality of cells and also has a terminate end cell which is one of said plurality of cells and which is positioned at an end of said structure of said semiconductor device, and
said passivation film is formed to locate adjacent to said conductive pattern of said terminate end cell over said barrier metal of said terminate end cell and also formed to cover said dielectric film outside said structure of said semiconductor device as exposed when patterning said metal layer.
36. The semiconductor device according to claim 32, wherein said cell includes a vertically structured semiconductor circuit element.
37. The semiconductor device according to claim 32, wherein
said electrode pattern of said cell is formed on or above one main surface of said semiconductor substrate, and
said cell includes another electrode pattern as formed on or above a remaining main surface of said semiconductor substrate.
38. The semiconductor device according to claim 32, further comprising:
a wire coupled by bonding to said electrode pattern of said cell.
39. The semiconductor device according to claim 32, further comprising:
a metal plate adhered to said electrode pattern of said cell.