1. A method of forming a filtering capacitor feedthrough assembly for an implantable active medical device comprising:
inserting a terminal pin into an aperture of a capacitor, the capacitor configured to be electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device;
disposing an electrically conductive continuous coil within the aperture between the terminal pin and the capacitor; and
fixing the continuous coil to the terminal pin and the capacitor, the continuous coil comprising an inner diameter defined by a plurality of coils, the terminal pin extending through the inner diameter of the continuous coil so that the plurality of coils circumferentially surround the terminal pin, the electrically conductive continuous coil mechanically securing and electrically coupling the terminal pin to the capacitor.
2. A method according to claim 1, wherein the fixing step comprises soldering the continuous coil to the terminal pin or capacitor.
3. A method according to claim 1, wherein fixing step comprises welding the continuous coil to the terminal pin or capacitor.
4. A method according to claim 1, wherein fixing step comprises adhering the continuous coil to the terminal pin or capacitor.
5. A method according to claim 1, wherein the disposing step comprises compressing the continuous coil between the terminal pin and the capacitor.
6. A method according to claim 1, wherein the disposing step comprise disposing two or more continuous coils within the aperture and between the terminal pin and the capacitor, the two or more continuous coils mechanically securing and electrically coupling the terminal pin to the capacitor.
7. A method according to claim 1, wherein the fixing step further comprises disposing a conductive adhesive, solder, or braze disposed within the aperture.
8. A method according to claim 1, wherein the aperture defines a ledge and the continuous coil is disposed on the ledge.
9. A method according to claim 1, further comprising disposing a second electrically conductive continuous coil between the capacitor and the electrically conductive feedthrough ferrule or housing of the implantable active medical device, the second electrically conductive continuous coil mechanically securing and electrically coupling the capacitor and the electrically conductive feedthrough ferrule or housing of the implantable active medical device.
10. A method of forming a filtering capacitor feedthrough assembly for an implantable active medical device comprising:
inserting a terminal pin into an aperture of a capacitor, the capacitor configured to be electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device;
disposing an electrically conductive continuous coil within the aperture between the terminal pin and the capacitor; and
fixing the continuous coil to the terminal pin, the continuous coil comprising an inner diameter defined by a plurality of coils, the terminal pin extending through the inner diameter of the continuous coil so that the plurality of coils circumferentially surround the terminal pin, the electrically conductive continuous coil mechanically securing and electrically coupling the terminal pin to the capacitor.
11. A method according to claim 10, wherein the fixing step comprises soldering the continuous coil to the terminal pin.
12. A method according to claim 10, wherein fixing step comprises welding the continuous coil to the terminal pin.
13. A method according to claim 10, wherein fixing step comprises adhering the continuous coil to the terminal pin.
14. A method according to claim 10, wherein the disposing step comprises compressing the continuous coil between the terminal pin and the capacitor.
15. A method according to claim 10, wherein the disposing step comprise disposing two or more continuous coils within the aperture and between the terminal pin and the capacitor, the two or more continuous coils mechanically securing and electrically coupling the terminal pin to the capacitor.
16. A method according to claim 10, wherein the fixing step further comprises disposing a conductive adhesive, solder, or braze disposed within the aperture.
17. A method of forming an active medical device comprising:
forming a filtering capacitor feedthrough assembly by:
inserting a terminal pin into an aperture of a capacitor, the capacitor configured to be electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device;
disposing an electrically conductive continuous coil within the aperture between the terminal pin and the capacitor; and
fixing the continuous coil to the terminal pin, the continuous coil comprising an inner diameter defined by a plurality of coils, the terminal pin extending through the inner diameter of the continuous coil so that the plurality of coils circumferentially surround the terminal pin, the electrically conductive continuous coil mechanically securing and electrically coupling the terminal pin to the capacitor;
attaching a lead connector and active medical device electronics to the filtering capacitor feedthrough assembly; and
hermetically sealing the active medical device electronics within the housing of the implantable active medical device.
18. A method according to claim 17, wherein the fixing step comprises soldering, welding or adhering the continuous coil to the terminal pin or capacitor.
19. A method according to claim 17, wherein the fixing step further comprises disposing a conductive adhesive, solder, or braze disposed within the aperture.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of reading data from and writing data to a memory device over a bus structure including a plurality of signal lines, comprising:
a. grouping the plurality of signal lines into two or more bi-directional and reconfigurable groups; and
b. transmitting data to and from the memory device over the groups of signal lines by specifying a selected group of the groups of signal lines and a current operation.
2. The method as claimed in claim 1 wherein the selected group and the current operation are specified over operation control input signal lines.
3. The method as claimed in claim 2 wherein the operation control input signal lines are provided to the memory device from a controller.
4. The method as claimed in claim 1 wherein the memory device is an SRAM.
5. The method as claimed in claim 1 wherein transmitting includes alternating groups of signal lines to complete a sequence of operations.
6. The method as claimed in claim 1 wherein the current operation includes one of a read operation, a write operation and a deselect operation.
7. The method as claimed in claim 6 wherein transmitting includes initiating read and write operations alternately between groups of signal lines except if:
a. a sequence of two or more consecutive read operations is followed immediately by a write operation, then a last read operation in the sequence is initiated to a same group of signal lines as a second to last read operation in the sequence; and
b. a sequence of a read operation followed immediately by two or more consecutive write operations, then a second write operation in the sequence is initiated to a same group of signal lines as a first write operation in the sequence.
8. A method of reading data from and writing data to a memory device over a bus structure including a plurality of signal lines, comprising:
a. grouping the plurality of signal lines into two or more bi-directional and reconfigurable groups, wherein each group of signal lines is capable of performing both read and write operations;
b. specifying control signals for a current operation, the control signals including a selected one of the groups of signal lines and the current operation; and
c. communicating data for the current operation over the selected group of signal lines in a direction dependent upon the current operation.
9. The method as claimed in claim 8 wherein the control signals are specified over operation control input signal lines.
10. The method as claimed in claim 9 wherein the operation control input signal lines are provided to the memory device from a controller.
11. The method as claimed in claim 8 wherein the memory device is an SRAM.
12. The method as claimed in claim 8 wherein communicating includes alternating groups of signal lines to complete a sequence of operations.
13. The method as claimed in claim 8 wherein the current operation includes one of a read operation, a write operation and a deselect operation.
14. The method as claimed in claim 13 wherein communicating includes initiating read and write operations alternately between groups of signal lines except if:
a. a sequence of two or more consecutive read operations is followed immediately by a write operation, then a last read operation in the sequence is initiated to a same group of signal lines as a second to last read operation in the sequence; and
b. a sequence of a read operation followed immediately by two or more consecutive write operations, then a second write operation in the sequence is initiated to a same group of signal lines as a first write operation in the sequence.
15. A bus structure configured for reading data from and writing data to a memory device, comprising n data signal lines, grouped into a plurality of bidirectional and reconfigurable groups.
16. The bus structure as claimed in claim 15 wherein each of the groups comprises m data signal lines.
17. The bus structure as claimed in claim 15 further comprising a plurality of operation control signal lines for communicating operation control signals specifying a selected one of the groups and a current operation.
18. The bus structure as claimed in claim 17 wherein the current operation includes one of a read operation, a write operation and a deselect operation.
19. The bus structure as claimed in claim 15 wherein the memory device is an SRAM.
20. The bus structure as claimed in claim 15 wherein each of the groups of data signal lines are capable of performing both read and write operations.
21. A memory device comprising an interface configured for coupling to a plurality of bidirectional and reconfigurable data signal lines and a plurality of operation control signal lines, wherein the data signal lines are configured for grouping into a plurality of groups, each of the groups of data signal lines capable of performing both read and write operations, and further wherein operation control signals are received on the operation control signal lines specifying a selected one of the groups of data signal lines and a current operation.
22. The memory device as claimed in claim 21 wherein the operation control signal lines are provided to the memory device from a controller.
23. The memory device as claimed in claim 21 wherein the memory device is an SRAM.
24. The memory device as claimed in claim 21 wherein the current operation includes one of a read operation, a write operation and a deselect operation.
25. A memory device comprising:
a. a data interface configured for coupling to a plurality of bidirectional and reconfigurable data signal lines, wherein the data signal lines are configured for grouping into a plurality of groups, each of the groups of data signal lines capable of performing both read and write operations; and
b. a control interface configured for coupling to a plurality of operation control signal lines for receiving operation control signals, wherein the operation control signals specify a selected one of the groups of data signal lines and a current operation.
26. The memory device as claimed in claim 25 wherein the operation control signal lines are provided to the memory device from a controller.
27. The memory device as claimed in claim 25 wherein the memory device is an SRAM.
28. The memory device as claimed in claim 25 wherein the current operation includes one of a read operation, a write operation and a deselect operation.
29. A memory system comprising:
a. a plurality of bidirectional and reconfigurable data signal lines configured for grouping into a plurality of groups, each of the groups of data signal lines capable of performing both read and write operations;
b. a plurality of operation control signal lines for transmitting operation control signals;
c. a memory controller including:
i. a controller data interface coupled to the plurality of data signal lines for transmitting and receiving data over the data signal lines; and
ii. a controller control interface coupled to the plurality of operation control signal lines for transmitting the operation control signals; and
d. a memory device including:
i. a device data interface coupled to the plurality of data signal lines for performing both read and write operations over the data signal lines: and
ii. a device control interface coupled to the plurality of operation control signal lines for receiving the operation control signals from the controller control interface, wherein the operation control signals specify a selected one of the groups of data signal lines and a current operation.
30. The memory system as claimed in claim 29 wherein the memory device is an SRAM.
31. The memory system as claimed in claim 29 wherein the current operation includes one of a read operation, a write operation and a deselect operation.