1. A method of forming a transistor including a gate electrode, the method comprising:
forming a sacrificial layer over a semiconductor substrate;
forming a patterning layer over the sacrificial layer;
patterning the patterning layer to form patterned structures;
forming spacers adjacent to sidewalls of the patterned structures;
removing the patterned structures;
etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate; and
filling a conductive material in the trenches in the semiconductor substrate to form gate electrodes.
2. The method of claim 1, wherein etching through the sacrificial layer and etching into the substrate also forms first through holes in the sacrificial layer, and wherein the conductive material also fills the first through holes in the sacrificial layer.
3. The method of claim 1, further comprising forming a hard mask layer over the semiconductor substrate before forming the sacrificial layer, the sacrificial layer being selectively etchable with respect to the hard mask layer.
4. The method of claim 3, further comprising etching through the hard mask layer using the patterned sacrificial layer as an etching mask to form second through holes in the hard mask layer and to form patterned hardmask portions, and wherein the conductive material also fills the second through holes in the hard mask layer.
5. The method of claim 4, further comprising covering an edge portion of the semiconductor substrate with portions of a resist material before etching so that the spacers and the portions of the resist material act as the etching mask.
6. The method of claim 2, further comprising modifying a surface portion of the conductive material to form modified surface portions.
7. The method of claim 4, further comprising covering sidewalls of the patterned hardmask with a cover layer.
8. The method of claim 6, wherein modifying the surface portion of the conductive material comprises oxidizing the surface of the conductive material.
9. The method of claim 1, further comprising forming a gate contact to the gate electrode, by defining an opening in a photoresist material over the semiconductor substrate, the opening having a greater width than a width of the trench.
10. The method of claim 1, further comprising forming a mesa contact to the semiconductor substrate material between adjacent trenches, by defining an opening in a photoresist material over the semiconductor substrate, the opening having a greater width than a distance between adjacent trenches.
11. The method of claim 1, further comprising forming a dielectric layer on a sidewall of the trench in the semiconductor substrate before filling the conductive material in the trenches.
12. The method of claim 1, further comprising forming components of a power device selected from the group consisting of insulated gate bipolar transistors, diodes, and field effect transistors.
13. The method of claim 1, further comprising forming mesa contacts to the semiconductor substrate between adjacent trenches and forming a conductive element electrically coupling the mesa contacts to each other.
14. The method of claim 1, further comprising forming gate contacts to the gate electrodes and forming a conductive element electrically coupling the gate contacts to each other.
15. A method for patterning a substrate, the method comprising:
forming a sacrificial layer over the substrate;
forming a patterning layer over the sacrificial layer;
patterning the patterning layer to form patterned structures;
forming spacers adjacent to sidewalls of the patterned structures;
removing the patterned structures;
etching through the sacrificial layer using the spacers as an etching mask and etching into the substrate, thereby forming first through holes in the sacrificial layer and trenches in the substrate; and
filling a fill material into the trenches in the substrate and in the first through holes in the sacrificial layer.
16. The method of claim 15, further comprising modifying a surface of the fill material to form modified surface portions.
17. The method of claim 16, wherein modifying the surface of the fill material comprises oxidizing the surface of the fill material.
18. The method of claim 15, wherein forming the trenches in the substrate and the first through holes in the sacrificial layer comprises:
etching the sacrificial layer using the spacers as an etching mask to form the first through holes and sacrificial structures in the sacrificial layer;
removing the spacers; and
etching the trenches into the substrate using the sacrificial structures as an etching mask.
19. The method of claim 18, further comprising forming a cover layer on sidewalls of the sacrificial structures before etching the trenches into the substrate.
20. A transistor comprising trenches in a semiconductor substrate, a gate electrode arranged in the trenches and mesas defined between adjacent trenches,
wherein the gate electrode comprises a first portion disposed over a main surface of the substrate and a second portion disposed below the main surface,
wherein a width of the first portion of the gate electrode is greater than a diameter of the second portion of the gate electrode, and
wherein a width of the mesas is between 50 to 500 nm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system comprising:
a host computer; and
a storage system coupled to the host computer via a network;
the storage system comprising:
a plurality of ports;
a storage controller; and
a plurality of logical volumes;
wherein the storage controller is configured to:
associate between the at least one of the plurality of ports and a golden image;
receive an access request from the host computer via a port that the host computer is connected thereto; and
transfer the access request between the port and the logical volume which stores a copy of the golden image associated with the port.
2. The system of claim 1, wherein the storage controller is further configured to check if the host computer is new access to the storage system when the access request is received.
3. The system of claim 2, wherein the storage controller is further configured to, if the host computer is new access to the storage system, check if there is a logical volume which stores a copy of a golden image associated with the port.
4. The system of claim 3, wherein, if there is no logical volume which stores a copy of the golden image associated with the port, the storage controller is further configured to:
create a logical volume based on the request;
copy a golden image data to the logical volume;
and allocate an internal path between the port and the logical volume.
5. The system of claim 1, wherein at least one of the plurality of ports is associated with a plurality of golden images.
6. The system of claim 1, wherein the golden image is associated with zone setting in SAN switch in the network.
7. The system of claim 5, further comprising a user interface whereby the user can select one of the plurality of golden images.
8. The system of claim 7, wherein the user interface comprises a dial which indicates the plurality of golden images to be selected by user.
9. A system comprising:
a host computer; and
a storage system coupled to the host computer via a network;
the storage system comprising:
a plurality of ports;
a storage controller; and
a plurality of logical volumes;
wherein, upon receiving a request, the storage controller configured to:
create a logical volume based on the request;
register a golden image data as a golden image;
associate at least one of the plurality of ports with the golden image;
copy the golden image data to at least one of the plurality of logical volumes;
and allocate an internal path between the at least one of the plurality of ports and the at least one of the plurality of the logical volumes.
10. The system of claim 9, wherein the storage controller is further configured to check if there is available capacity for logical volumes in the storage system.
11. The system of claim 9, wherein the golden image is created by installing a server operation system or an application.
12. The system of claim 9, wherein the golden image is a SAN boot image.
13. The system of claim 9, wherein the golden image is at least one of virtual disk files that are used to provision at least one of virtual machines.
14. The system of claim 9, wherein the storage controller further comprises a memory which maintains a port attribute management table.
15. The system of claim 9, wherein the port attribute management table comprises information of a port ID and a golden image name.
16. The system of claim 9, wherein the storage controller is further configured to, if there is an available port for the registered golden image, associate the available port with the registered golden image.
17. The system of claim 9, wherein the storage controller is further configured to receive a golden image copy request which comprises identification of golden image and required number of copies to be created for the golden image.
18. The system of claim 9, wherein the storage controller further comprises a memory which maintains a path management table.
19. The system of claim 18, wherein the path management table comprises information of a logical volume ID and a port ID.
20. The system of claim 18, wherein the storage controller further updates the port attribute management table when the internal path between the one of the plurality of ports and the one of the plurality of the logical volumes is allocated.