1. A non-volatile memory element comprising:
a semiconductor substrate;
a first impurity diffusion region and a second impurity diffusion region provided on said semiconductor substrate;
a memory gate, with a charge accumulation section, provided on a part of a channel region disposed between said first and second impurity diffusion regions and;
a control gate provided on another part of said channel region adjacent to said memory gate interposed with an insulating film, wherein;
electric potentials of said memory gate and said control gate are controlled independently; and
said memory gate has a curved surface on a side in contact with said control gate, said curved surface being convex towards said control gate, said control gate being provided on said curved surface interposed with said insulating film.
2. The non-volatile memory element as defined in claim 1 wherein said control gate has a cross sectional shape along that a longitudinal direction of said gate becomes narrower towards the top and away from said semiconductor substrate.
3. The non-volatile memory element as defined in claim 1 wherein a side of said control gate opposite to the one adjacent to said memory gate has a curved surface and is convex towards the outside.
4. The non-volatile memory element as defined in claim 1 wherein said control gate is formed by etching back.
5. The non-volatile memory element as defined in claim 1 wherein said memory gate is formed by etching back and said control gate is provided laterally on a side formed by etching back.
6. The non-volatile memory element as defined in claim 1 wherein the height of said control gate is shorter than that of said memory gate.
7. The non-volatile memory element as defined in claim 1 wherein said memory gate comprises a charge accumulation section, a first conductive film containing a first conductivity type impurity provided on said charge accumulation section, and a second conductive film of a first conductivity type provided on said first conductive film and;
said first conductive film has an impurity concentration different from the impurity concentration of said second conductive film.
8. The non-volatile memory element as defined in claim 1 wherein said memory gate has an electrode width not less than 20 nm and not more than 200 nm.
9. The non-volatile memory element as defined in claim 1 wherein said charge accumulation section comprises a silicon nitride layer, and insulating layers are provided above and below said silicon nitride layer sandwiching the silicon nitride layer.
10. The non-volatile memory element as defined in claim 1 wherein said charge accumulation section comprises multiple dot-shaped dielectric materials disposed separated from one another, and insulating layers are provided above and below said dot-shaped dielectric materials sandwiching said dot-shaped dielectric materials.
11. A semiconductor device comprising: a pair of the non-volatile memory elements as defined in claim 1 provided in parallel, wherein said second impurity diffusion region shared by the non-volatile memory elements is located in a region sandwiched by these non-volatile memory elements; and
a conductive material is embedded in an area of said second impurity diffusion region sandwiched by said pair of the non-volatile memory elements.
12. A process for manufacturing a non-volatile memory element comprising the steps of:
forming a film comprising a charge accumulation section on a semiconductor substrate, and a sacrificial film in a prescribed region on the film comprising said charge accumulation section;
forming a first conductive film that covers said sacrificial film;
forming first and second memory gates provided apart from each other by etching back said first conductive film and leaving said first conductive film on the side of said sacrificial film;
forming an insulating film that covers the sides of said first and second memory gates opposite to the one on which said sacrificial film is provided;
forming a second conductive film over the whole surface of the substrate; and
forming control gates adjacent to said memory gates interposed with said insulating film by etching back said second conductive film and leaving said second conductive film on the sides of said first and second memory gates located towards the outside as viewed from said sacrificial film.
13. A process for manufacturing a non-volatile memory element comprising the steps of:
forming a film comprising a charge accumulation section on a semiconductor substrate and forming a sacrificial film with an opening on the film comprising said charge accumulation section;
forming a first conductive film that covers said sacrificial film;
forming a first and second memory gates provided apart from each other by etching back said first conductive film and leaving said first conductive film on the side of an opening of said sacrificial film along a longitudinal direction of said gate;
forming an insulating film that covers sides of said first and second memory gates opposite to the one on which said sacrificial film is provided, and forming an impurity diffusion region by injecting impurities into an area between said first and second memory gates on the substrate surface;
forming a conductive film over said impurity diffusion region;
forming an insulating film that covers sides of said first and second memory gates opposite to the one on which said conductive film is provided after said sacrificial film is removed;
forming a second conductive film on the whole surface of the substrate; and
forming control gates each adjacent to each of said memory gates, respectively, interposed with said insulating film by etching back said second conductive film and leaving said second conductive film on the sides of said first and second memory gates located towards the outside as viewed from said conductive film.
14. A memory element comprising:
a semiconductor substrate;
a first impurity diffusion region and a second impurity diffusion region provided on said semiconductor substrate;
a memory gate, with a charge accumulation section, provided on a part of a channel region disposed between said first and second impurity diffusion regions and;
a control gate provided on another part of said channel region adjacent to said memory gate interposed with an insulating film, wherein;
electric potentials of said memory gate and said control gate are controlled independently;
said memory gate has a curved surface on a side in contact with said control gate, said curved surface being convex towards said control gate, said control gate being provided on said curved surface interposed with said insulating film,
said control gate having a cross sectional shape along that a longitudinal direction of said gate becomes narrower towards the top and away from said semiconductor substrate
15. The memory element as defined in claim 14 wherein a side of said control gate opposite to the one adjacent to said memory gate has a curved surface and is convex towards the outside.
16. The memory element as defined in claim 15 wherein said control gate is formed by etching back.
17. The memory element as defined in claim 16 wherein said memory gate is formed by etching back and said control gate is provided laterally on a side formed by etching back.
18. The memory element as defined in claim 17 wherein the height of said control gate is shorter than that of said memory gate.
19. The memory element as defined in claim 14 wherein said memory gate comprises a charge accumulation section, a first conductive film containing a first conductivity type impurity provided on said charge accumulation section, and a second conductive film of a first conductivity type provided on said first conductive film and;
said first conductive film has an impurity concentration different from the impurity concentration of said second conductive film.
20. The memory element as defined in claim 14 wherein said charge accumulation section comprises multiple dot-shaped dielectric materials disposed separated from one another, and insulating layers are provided above and below said dot-shaped dielectric materials sandwiching said dot-shaped dielectric materials.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An architecture for a fuel cell power conditioning system comprising:
a first fuel cell segment arranged to have a positive terminal and a negative terminal;
a first DCDC converter, an input of which is connected to the positive terminal of the first fuel cell segment and the negative terminal of the first fuel cell segment; and
a second DCDC converter, an input of which is connected to the positive terminal of the first fuel cell segment and the negative terminal of the first fuel cell segment;
a second fuel cell segment arranged to have a positive terminal and a negative terminal, wherein the positive terminal of the second fuel cell segment is electrically connect to the negative terminal of the first fuel cell segment;
a third DCDC converter, an input of which is connected to the positive terminal of the second fuel cell segment and the negative terminal of the second fuel cell segment; and
a fourth DCDC converter, an input of which is connected to the positive terminal of the second fuel cell segment and the negative terminal of the second fuel cell segment;
wherein the positive output terminals of the first and third DCDC converters are connected to a common positive voltage bus,
wherein the negative output terminals of the second and fourth DCDC converters are connected to a common negative voltage bus, and
wherein the negative output terminals of the of the first and third DCDC converters and the positive output terminals of the second and fourth DCDC converters are connected to a neutral bus.
2. The architecture of claim 1, wherein the first and third DCDC converters convert their respective input voltage to the same positive output voltage and wherein the second and fourth DCDC converters convert their respective input voltage to the same negative output voltage.
3. The architecture of claim 1, wherein
the first and third DCDC converters have different conversion ratios; and
the second and fourth DCDC converters have different conversion ratios.
4. The architecture of claim 1 wherein the common positive voltage bus and the common negative voltage bus are each electrically connected to the common neutral bus via a respective capacitor.
5. The architecture of claim 1, further comprising a DCAC converter comprising a first input electrically connected to the common positive voltage bus, a second input connected to the common neutral bus, and a third input connected to the common negative voltage bus.
6. The architecture of claim 2, wherein the DCAC converter produces a three-phase current output and a neutral output from the first, second and third inputs.
7. The architecture of claim 2, wherein power ripple currents generated by the first and the third DCDC converters are approximately 180 degrees out of phase and are substantially cancelled.